600 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
648364 | 05/10/2022 | Public |
Signal Description
Signal Name | Type | Description |
---|---|---|
PCH_JTAG_TCK | I/O | Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. |
PCH_JTAG_TMS | I/OD | Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. |
PCH_JTAG_TDI | I/OD | Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. |
PCH_JTAG_TDO | I/OD | Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. |
PCH_JTAGX | I/O | This pin is used to support merged debug port topologies. |
DBG_PMODE | O | ITP Power Mode Indicator. This signal is used to transmit processor and PCH power/reset information to the Debugger. |
I | This pin is used for debug support | |
O | This pin is used for debug support
| |
PREQ# | I/OD | |
PRDY# | I/OD |