Fixed I/O Address Ranges
The following table shows the Fixed I/O decode ranges from the processor perspective. For each I/O range, there may be separate behavior for reads and writes.
DMI cycles that go to target ranges that are marked as Reserved will be handled by the PCH; writes are ignored and reads will return all 1 s. The P2SB will claim many of the fixed I/O accesses and forward those transactions over IOSF-SB to their functional target.
Address ranges that are not listed or marked Reserved are NOT positively decoded by the PCH (unless assigned to one of the variable ranges) and will be internally terminated by the PCH.
Fixed I/O Ranges Decoded by PCH
| I/O Address | Read Target | Write Target | Internal Unit (unless[E]: External)2 | Separate Enable/Disable |
|---|
| 20h – 21h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 24h – 25h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 28h – 29h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 2Ch – 2Dh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 2Eh – 2Fh | Super I/O | Super I/O | [E] Forwarded to eSPI | Yes. ESPI_IOD_IOE.SE |
| 30h – 31h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 34h – 35h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 38h – 39h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 3Ch – 3Dh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 40h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 42h – 43h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 4E – 4F | Microcontroller | Microcontroller | [E] Forwarded to eSPI | Yes. ESPI_IOD_IOE.ME2 |
| 50h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 52h – 53h | Timer/Counter | Timer/Counter | 8254 Timer | None |
| 60h | Keyboard Controller | Keyboard Controller | [E] Forwarded to eSPI | Yes, with 64h. ESPI_IOD_IOE.KE |
| 61h | NMI Controller | NMI Controller | Processor I/F | None |
| 62h | Microcontroller | Microcontroller | [E] Forwarded to eSPI | Yes, with 66h. ESPI_IOD_IOE.ME1 |
| 63h | NMI Controller 1 | NMI Controller 1 | I/F | Yes, alias to 61h. GIC.P61AE |
| 64h | Keyboard Controller | Keyboard Controller | [E] Forwarded to eSPI | Yes, with 60h. ESPI_IOD_IOE.KE |
| 65h | NMI Controller 1 | NMI Controller 1 | Processor I/F | Yes, alias to 61h. GIC.P61AE |
| 66h | Microcontroller | Microcontroller | [E] Forwarded to eSPI | Yes, with 62h. ESPI_IOD_IOE.ME1 |
| 67h | NMI Controller 1 | NMI Controller 1 | Processor I/F | Yes, alias to 61h. GIC.P61AE |
| 70h | RTC Controller | NMI and RTC Controller | RTC | None |
| 71h | RTC Controller | RTC Controller | RTC | None |
| 72h | RTC Controller | RTC Controller | RTC | None. Alias to 70h if RC.UE4=0, else 72h |
| 73h | RTC Controller | RTC Controller | RTC | None. Alias to 71h if RC.UE=’0’, else 73h |
| 74h | RTC Controller | RTC Controller | RTC | None |
| 75h | RTC Controller | RTC Controller | RTC | None |
| 76h – 77h | RTC Controller | RTC Controller | RTC | None. Alias to 70h-71h if RC.UE=0, else 76h-77h |
| 80h3 | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 84h – 86h | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 88h | eSPI or PCIe | eSPI or PCIe | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 8Ch – 8Eh | eSPI or PCIe | eSPI or PCIe* | Read: [E] eSPI or PCIe Write: [E] eSPI or [E] PCIe | None. PCIe if GCS.RPR=’1’, else eSPI |
| 90h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 80h |
| 92h | Reset Generator | Reset Generator | Processor I/F | None |
| 94h – 96h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 8xh |
| 98h | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 88h |
| 9Ch – 9Eh | eSPI | eSPI | Read: [E] eSPI Write: [E] eSPI | None. Alias to 8xh |
| A0h – A1h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| A4h – A5h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| A8h – A9h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| ACh – ADh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| B0h – B1h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| B2h – B3h | Power Management | Power Management | Power Management | None |
| B4h – B5h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| B8h – B9h | Interrupt Controller | Interrupt Controller | Interrupt | None |
| BCh – BDh | Interrupt Controller | Interrupt Controller | Interrupt | None |
| 200h – 207h | Gameport Low | Gameport Low | Forwarded to eSPI | Yes. ESPI_CS1IORE.LGRE |
| 208h – 20Fh | Gameport High | Gameport High | Forwarded to eSPI | Yes. ESPI_CS1IORE.HGRE |
| 4D0h – 4D1h | Interrupt Controller | Interrupt Controller | Interrupt Controller | None |
| CF9h | Reset Generator | Reset Generator | Interrupt controller | None |
- Only if the Port 61 Alias Enable bit (GIC.P61AE) bit is set. Otherwise, the cycle is internally terminated by the PCH.
- Destination of eSPI when eSPI Disabled pin strap is 0.
- This includes byte, word or double-word (DW) access at I/O address 80h
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