Host Controller
The host SMBus controller supports up to 100 kHz clock speed and is clocked by the RTC clock.
The PCH can perform SMBus messages with either Packet Error Checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in SW. The SMBus host controller logic can automatically append the CRC byte if configured to do so.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the Host Notify command (which is actually a received message).
The PCH SMBus host controller checks for parity errors as a target. If an error is detected, the detected parity error bit in the PCI Status Register is set.
Host Controller Operation Overview
The SMBus host controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt, if enabled.
The host controller supports eight command protocols of the SMBus interface (Refer to the System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Block Write–Block Read Process Call.
The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host controller performs the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction is completed. Once a START command has been issued, the values of the “active registers” (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status message (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus host controller updates all registers while completing the new command.
Slave functionality, including the Host Notify protocol, is available on the SMBus pins.
Using the SMB host controller to send commands to the PCH SMB slave port is not supported.
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set.
If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set after the PCH forces a time - out. In addition, if KILL bit is set during the CRC cycle, both the CRCE and DEV_ERR bits will also be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0 when running this command. Refer to Section 5.5.1 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Send Byte/Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent. For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this command.
The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. Refer to the Sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Write Byte/Word
The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a Write Byte/Word command, the Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a Write Word command. Software must force the I2C_EN bit to 0 when running this command. Refer to Section 5.5.4 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Read Byte/Word
Reading data is slightly more complicated than writing data. First the PCH must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. Software must force the I2C_EN bit to 0 when running this command.
When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. Refer to Section 5.5.5 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Process Call
The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition.
When programmed for the Process Call command, the PCH transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers.
The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. Refer to Section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
- For process call command, the value written into bit 0 of the Transmit Slave Address Register needs to be 0.
- If the I2C_EN bit is set, the protocol sequence changes slightly, the Command Code (Bits 18:11 in the bit sequence) are not sent. As a result, the slave will not acknowledge (Bit 19 in the sequence).
Block Read/Write
The PCH contains a 32 - byte buffer for read and write data which can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32 - byte buffer is filled with write data before transmission, and filled with read data on reception. In the PCH, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received.
The byte count field is transmitted but ignored by the PCH as software will end the transfer after all bytes it cares about have been sent or received.
For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to 0 when running this command.
The block write begins with a slave address and a write condition. After the command code the PCH issues a byte count describing how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total data sent being the value stored in the Data0 Register.
On block read commands, the first byte received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte register. Refer to section 5.5.7 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
I2C* Read
This command allows the PCH to perform block reads to certain I2C devices, such as serial E2PROMs. The SMBus Block Read supports the 7 - bit addressing mode only.
However, this does not allow access to devices using the I2C “Combined Format” that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips.
For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0.
The format that is used for the command is shown in the table below:
| Bit | Description |
|---|---|
| 1 | Start |
| 8:2 | Slave Address – 7 bits |
| 9 | Write |
| 10 | Acknowledge from slave |
| 18:11 | Send DATA1 register |
| 19 | Acknowledge from slave |
| 20 | Repeated Start |
| 27:21 | Slave Address – 7 bits |
| 28 | Read |
| 29 | Acknowledge from slave |
| 37:30 | Data byte 1 from slave – 8 bits |
| 38 | Acknowledge |
| 46:39 | Data byte 2 from slave – 8 bits |
| 47 | Acknowledge |
| – | Data bytes from slave/Acknowledge |
| – | Data byte N from slave – 8 bits |
| – | NOT Acknowledge |
| – | Stop |
The PCH will continue reading data from the peripheral until the NAK is received.
Block Write – Block Read Process Call
The block write - block read process call is a two - part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message. If a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.
The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0.
The combined data payload must not exceed 32 bytes. The byte length restrictions of this process call are summarized as follows:
The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write - Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.
Refer to Section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The PCH continuously monitors the SMBDATA line. When the PCH is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the PCH will stop transferring data.
If the PCH detects that it has lost arbitration, the condition is called a collision. The PCH will set the BUS_ERR bit in the Host Status Register, and if enabled, generates an interrupt or SMI#. The processor is responsible for restarting the transaction.
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the PCH as an SMBus master would like. They have the capability of stretching the low time of the clock. When the PCH attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time.
The PCH monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data.
Bus Timeout (PCH as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge or holds the clock lower than the allowed Timeout time, the transaction will time out. The PCH will discard the cycle and set the DEV_ERR bit. The timeout minimum is 25 ms (800 RTC clocks). The Timeout counter inside the PCH will start after the first bit of data is transferred by the PCH and it is waiting for a response.
The 25 - ms Timeout counter will not count under the following conditions:
Interrupts/SMI#
The PCH SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN bit.
The three tables below, specify how the various enable bits in the SMBus function control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables are additive, which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur.
| Event | INTREN (Host Control I/O Register, Offset 02h, Bit 0) | SMB_SMI_EN (Host Configuration Register, D31:F4:Offset 40h, Bit 1) | SMBALERT_DIS (Slave Command I/O Register, Offset 11h, Bit 2) | Result |
|---|---|---|---|---|
| SMBALERT# asserted low (always reported in Host Status Register, Bit 5) | X | X | X | Wake generated |
| X | 1 | 0 | Slave SMI# generated (SMBUS_SMI_STS) | |
| 1 | 0 | 0 | Interrupt generated |
| Event | INTREN (Host Control I/O Register, Offset 02h, Bit 0) | SMB_SMI_EN (Host Configuration Register, D31:F4:Offset 40h, Bit 1) | Event |
|---|---|---|---|
| Slave Write to Wake/SMI# Command | X | X | Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS). |
| Slave Write to SMLINK_SLAVE_SMI Command | X | X | Slave SMI# generated when in the S0 state (SMBUS_SMI_STS) |
| Any combination of Host Status Register [4:1] asserted | 0 | X | None |
| 1 | 0 | Interrupt generated | |
| 1 | 1 | Host SMI# generated |
| HOST_NOTIFY_INTREN (Slave Control I/O Register, Offset 11h, Bit 0) | SMB_SMI_EN (Host Configuration Register, D31:F4:Off40h, Bit 1) | HOST_NOTIFY_WKEN (Slave Control I/O Register, Offset 11h, Bit 1) | Result |
|---|---|---|---|
| 0 | X | 0 | None |
| X | X | 1 | Wake generated |
| 1 | 0 | X | Interrupt generated |
| 1 | 1 | X | Slave SMI# generated (SMBUS_SMI_STS) |
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates and drives CRC at the end of the transmitted packet for write cycles, and will check the CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host Control register if this bit is set, or unspecified behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status register at Offset 0Ch will be set.