Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately after Reset1

S4/S5

Deep Sx

SPI0_​CLK

Primary

Internal Pull-down

Driven Low

Driven Low

OFF

SPI0_​MOSI

Primary

Hi-Z2

Internal PU, then Driven Low

Driven Low

OFF

SPI0_​MISO

Primary

Hi-Z

Internal Pull-up

Internal Pull-up

OFF

SPI0_​CS0#

Primary

Hi-Z

Driven High

Driven High

OFF

SPI0_​CS1#

Primary

Hi-Z

Driven High

Driven High

OFF

SPI0_​CS2#

Primary

Hi-Z

Driven High

Driven High

OFF

SPI0_​IO[3:2]

Primary

Hi-Z2

Internal Pull-up

Internal Pull-up

OFF

Notes:
  1. During reset refers to when RSMRST# is asserted.
  2. SPI0_​MOSI, SPI0_​IO[3:2] also function as strap pins. The actual pin state during Reset is dependent on the platform Pull-up/Pull-down resistor.