Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

I/O Signal Planes and States

Power Planes and States for Testability Signals

Signal Name

Power Plane

Resistors

During Reset1

Immediately after Reset1

S4/S5

Deep Sx

PCH_​TCK

Primary

Strong Internal Pull-Down

L

L

L

Off

PCH_​TMS

Primary

Internal Pull-Up

H

H

H

Off

PCH_​TDI

Primary

Internal Pull-Up

H

H

H

Off

PCH_​TDO

Primary

External Pull-Up

Z

Z

Z

Off

PCH_​JTAGX1

Primary

Internal Strong Pull-Up (as TDO Input),

Internal Strong Pull-Down (as TCK Output)

H

H/L

H/L

Off

DBG_​PMODE

Primary

Internal Pull-Up

H

H

H

Off

Notes:
  1. This signal is used in common JTAG topology to take in last device's TDO to DCI. The only planned supported topology is the Shared Topology. Thus, this pin will operate as TCK mode.
  2. Reset reference for primary well pins is RSMRST#.