Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

Power Domains and Management

ISH Power Management

The various functional blocks within the ISH are all on the primary power plane within the PCH. The ISH is only intended for use during S0 and S0ix states. There is no support for operation in S4, or S5 states. Thus, the system designer must ensure that the inputs to the ISH signals are not driven high while the PCH is in S5 state.

The unused banks of the ISH SRAM can be power-gated by the ISH Firmware.

External Sensor Power Management

External sensors can generally be put into a low power state through commands issued over the I/O interface (I2C). Refer to the datasheets of the individual sensors to obtain the commands to be sent to the peripheral.