Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

Power Management Sub-state

S0ix State Enable

If a platform wants to disable certain S0ix states, BIOS can do so by modifying the LPM_​EN register. The mapping of S0ix states to bits in the LPM_​EN register are given below:

LPM_​EN Register Mapping

Bit Number

S0ix State

Required Implementation1

0

S0i2.0

None2

1

S0i2.1

None2

2

S0i2.2

EXT_​PWR_​GATE# controlled FET to gate internal power plane for the HSIO core and suspend logic.

3

S0i3.0

None2

4

S0i3.1

None2

5

S0i3.2

None2

6

S0i3.3

EXT_​PWR_​GATE# controlled FET to gate internal power plane for the HSIO core and suspend logic.

Notes:

  1. Other board capabilities such as power control for RTD3 cold may be implicitly required to satisfy requirements.
  2. For external bypass voltage selection, VNN_​CTRL and V1P05_​CTRL can be used to select the external bypass.

Power Management Sub-State

Base State

Sub-state

Internal Power Plane for Internal Units that not required during S0ix

Internal Power Plane for the HSIO Core and Suspend Logic

Internal Power Plane for Gated SRAMs and Integrated System Clock PLLs

S0i2.0

S0i2.1

OFF

ON

ON

S0i2.2

OFF

OFF

ON

S0i3.0

S0i3.1

OFF

ON

ON

S0i3.2

OFF

ON

ON

S0i3.3

OFF

OFF

ON

Note:S0ix.0 is a base state when all power planes are on. For S0i3.2, and S0i3.3, the internal active power planes will be margined down from 1.05 V to 0.95 V.