Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
Private Configuration Space Target Port ID
The PCH incorporates a wide variety of devices and functions. The registers within these devices are mainly accessed through the primary interface, such as PCI configuration space and IO/MMIO space. Some devices also have registers that are distributed within the PCH Private Configuration Space at individual endpoints (Target Port IDs) which are only accessible through the PCH Sideband Interface. These PCH Private Configuration Space Registers can be addressed via SBREG_BAR or through SBI Index Data pair programming.
| PCH Device/Function Type | Target Port ID |
|---|---|
| OPI Configuration | 88h |
| FIA (Flexible I/O Adapter) Configuration | CFh |
| General Purpose I/O (GPIO) Community 0 | 6Eh |
| General Purpose I/O (GPIO) Community 1 | 6Dh |
| General Purpose I/O (GPIO) Community 2 | 6Ch |
| General Purpose I/O (GPIO) Community 4 | 6Ah |
| General Purpose I/O (GPIO) Community 5 | 69h |
| USB 3.2 Gen 1x1 Dual Role (xDCI) | 71h |
| DCI | B8h |
| PCIe* Controller #1 (SPA) | 80h |
| PCIe Controller #2 (SPB) | 81h |
| PCIe Controller #3 (SPC) | 82h |
| SATA | D9h |
| SMBus | C6h |
| eSPI / SPI | 72h |
| xHCI | 70h |
| CNVi | 73h |
| HSIO Strap Configuration | 89h |
| ISH Controller | BEh |
| Real Time Clock (RTC) | C3h |
| Processor Interface, 8254 Timer, HPET, APIC | C4h |
| USB 2.0 | CAh |
| UART | CBh |
| Integrated Clock Controller (ICC) | DCh |
| General Purpose I/O (GPIO) Community 3 | 6Bh |
| USB Dual Role | E5h |
| Intel® Trace Hub | B6h |