GPIO fixed functions (Signals for Integrated Connectivity (CNVi) and Discrete Connectivity (CNVd) functions)

GPP_​A7 / I2S2_​SCLK / DMIC_​CLK_​A0

I/O

For CNVi: Unused

For discrete connectivity with UART host support: Optional Bluetooth* I²S bus clock

GPP_​F4 / CNV_​RF_​RESET#

I/O

For CNVi: RF companion (CRF) reset signal, active low. Require a 75 kohm Pull-Down on platform/motherboard level. It is recommended not to use it for bootstrapping during early Platform init flows.

For discrete connectivity with UART host support: Optional Bluetooth* I²S bus sync

GPP_​A9 / I2S2_​TXD / MODEM_​CLKREQ / CRF_​XTAL_​CLKREQ / DMIC_​CLK_​A1

O

For CNVi: Clock request signal. Used to request the RF companion clock (38.4 MHz Ref clock). In PCH this function is not used, BUT this signal is also used for CNVi Init flow, so it must be connected on platform level even when clk sharing ability is not used/feasible.

Intel^® 500 Series platforms are not supporting the shared clk (38.4 MHz clk)

GPP_​F0 / CNV_​BRI_​DT / UART0_​RTS#

O

For CNVi: BRI bus TX.

For discrete connectivity with UART host support: Bluetooth* UART RTS#

GPP_​F1 / CNV_​BRI_​RSP / UART0_​RXD

I

For CNVi: BRI bus RX.

For discrete connectivity with UART host support: Bluetooth* UART RXD

GPP_​F2 / CNV_​RGI_​DT / UART0_​TXD

O

For CNVi: RGI bus TX.

For discrete connectivity with UART host support: Bluetooth* UART TXD

GPP_​F3 / CNV_​RGI_​RSP / UART0_​CTS#

I

For CNVi: RGI bus RX.

For discrete connectivity with UART host support: Bluetooth* UART CTS#

GPP_​F6 / CNV_​PA_​BLANKING

I/O

For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal. Used to be co-existence signal for external GNSS solution

GPP_​H8 / I2C4_​SDA / CNV_​MFUART2_​RXD

I

For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal (Input)

GPP_​H9 / I2C4_​SCL / CNV_​MFUART2_​TXD

O

For CNVi and discrete connectivity : Optional WLAN/Bluetooth* WWAN co-existence signal (Output)

Fixed special purpose I/O

CNVi_​WT_​CLKP

O

CNVio bus TX CLK+

CNVi_​WT_​CLKN

O

CNVio bus TX CLK-

CNVi_​WT_​D0P

O

CNVio bus Lane 0 TX+

CNVi_​WT_​D0N

O

CNVio bus Lane 0 TX-

CNVi_​WT_​D1P

O

CNVio bus Lane 1 TX+

CNVi_​WT_​D1N

O

CNVio bus Lane 1 TX-

CNVi_​WR_​CLKP

I

CNVio bus RX CLK+

CNVi_​WR_​CLKN

I

CNVio bus RX CLK-

CNVi_​WR_​D0P

I

CNVio bus Lane 0 RX+

CNVi_​WR_​D0N

I

CNVio bus Lane 0 RX-

CNVi_​WR_​D1P

I

CNVio bus Lane 1 RX+

CNVi_​WR_​D1N

I

CNVio bus Lane 1 RX-

CNVi_​WT_​RCOMP

O

Wi-Fi* DPHY RCOMP, analog connection point for an external bias resistor to ground

Selectable special purpose I/O

USB2P_​10

I/O

Bluetooth* USB host bus (positive) for discrete connectivity. Optional to connect to a Bluetooth* USB+ pin on the Bluetooth* module. Port 10 is the recommended port but other USB 2.0 ports can be selected for this function.

USB2N_​10

I/O

Bluetooth* USB host bus (negative) for discrete connectivity. Optional to connect to a Bluetooth* USB+ pin on the Bluetooth* module. Port 10 is the recommended port but other USB 2.0 ports can be selected for this function.

PCIE12_​TXP / SATA1_​TXP

O

Wi-Fi* PCIe* host bus TX (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PERp0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

PCIE12_​TXN / SATA1_​TXN

O

Wi-Fi* PCIe* host bus TX (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PERn0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

PCIE12_​RXP / SATA1_​RXP

I

Wi-Fi* PCIe* host bus RX (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PETp0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

PCIE12_​RXN / SATA1_​RXN

I

Wi-Fi* PCIe* host bus RX (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* PETn0 pin on the Wi-Fi* module. This is the recommended port but other PCIe* ports can be selected for this function.

CLKOUT_​PCIE_​P3

O

Wi-Fi* PCIe* host bus clock (positive) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* REFCLKp pin on the Wi-Fi* module. This is the recommended clock signal but other PCIe* clocks can be selected for this function.

CLKOUT_​PCIE_​N3

O

Wi-Fi* PCIe* host bus clock (negative) for discrete connectivity. Optional to connect to a Wi-Fi* PCIe* REFCLKp pin on the Wi-Fi* module. This is the recommended clock signal but other PCIe* clocks can be selected for this function.

CL_​RST#

O

Wi-Fi* CLINK host bus reset for discrete connectivity with CLINK support (Intel^® vPro™). Optional to connect to a Wi-Fi* CLINK reset pin on the Intel^® vPro™ Wi-Fi* module.

CL_​DATA

I/O

Wi-Fi* CLINK host bus data for discrete connectivity with CLINK support (Intel^® vPro™). Optional to connect to a Wi-Fi* CLINK data pin on the Intel^® vPro™ Wi-Fi* module.

CL_​CLK

O

Wi-Fi* CLINK host bus clock for discrete connectivity with CLINK support (Intel^® vPro™). Optional to connect to a Wi-Fi* CLINK clock pin on the Intel^® vPro™ Wi-Fi* module.