Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

Signal Description

Display is divided between processor and PCH. The processor houses memory interface, display planes, pipes, and digital display interfaces/ports while the PCH has transcoder and analog display interface or port.

The PCH integrates digital display side band signals DDC bus, and Hot-Plug Detect signals even though digital display interfaces are moved to processor. There are two pairs of DDC Clock/Data, and Hot-Plug Detect signals on the PCH that correspond to digital display interface/ports.

The DDC (Digital Display Channel) bus is used for communication between the host system and display. Six pairs of DDC (DDP*_​CTRLCLK and DDP*_​CTRLDATA) signals exist on the PCH that correspond to two digital ports on the processor. DDC follows I2C protocol.

The Hot-Plug Detect (HPD) signal serves as an interrupt request for the sink device for DisplayPort* and HDMI*. It is a 3.3 V tolerant signal pin on the PCH.

Digital Display Signals

Name

Type

Description

GPP_​E14 / DDSP_​HPDA / DISP_​MISCA

I

Display Port A: HPD Hot-Plug Detect

GPP_​A18 / DDSP_​HPDB / DISP_​MISCB / I2S4_​RXD

I

Display Port B: HPD Hot-Plug Detect

GPP_​A19 / DDSP_​HPD1 / DISP_​MISC1 / I2S5_​SCLK

I

TCP Port 1: HPD Hot-Plug Detect

GPP_​A20 / DDSP_​HPD2 / DISP_​MISC2 / I2S5_​SFRM

I

TCP Port 2: HPD Hot-Plug Detect

GPP_​A14 / USB_​OC1# / DDSP_​HPD3 / I2S3_​RXD / DISP_​MISC3 / DMIC_​CLK_​B1

I

TCP Port 3: HPD Hot-Plug Detect

GPP_​A15 / USB_​OC2# / DDSP_​HPD4 / DISP_​MISC4 / I2S4_​SCLK

I

TCP Port 4: HPD Hot-Plug Detect

GPP_​E22 / DDPA_​CTRLCLK /DNX_​FORCE_​RELOAD

I/O

Display Port A: Control Clock

GPP_​E23 / DDPA_​CTRLDATA

I/O

Display Port A: Control Data

GPP_​H16 / DDPB_​CTRLCLK / PCIE_​LNK_​DOWN

I/O

Display Port B: Control Clock

GPP_​H17 / DDPB_​CTRLDATA

I/O

Display Port B: Control Data

GPP_​E18 / DDP1_​CTRLCLK / TBT_​LSX0_​TXD / BSSB_​LS0_​RX

I/O

TCP Port 1: Control Clock

GPP_​E19 / DDP1_​CTRLDATA / TBT_​LSX0_​RXD / BSSB_​LS0_​TX

I/O

TCP Port 1: Control Data

GPP_​E20 / DDP2_​CTRLCLK / TBT_​LSX1_​TXD / BSSB_​LS1_​RX

I/O

TCP Port 2: Control Clock

GPP_​E21 / DDP2_​CTRLDATA / TBT_​LSX1_​RXD / BSSB_​LS1_​TX

I/O

TCP Port 2: Control Data

GPP_​D9 / ISH_​SPI_​CS# / DDP3_​CTRLCLK / TBT_​LSX2_​TXD / BSSB_​LS2_​RX / GSPI2_​CS0#

I/O

TCP Port 3: Control Clock

GPP_​D10 / ISH_​SPI_​CLK / DDP3_​CTRLDATA / TBT_​LSX2_​RXD / BSSB_​LS2_​TX / GSPI2_​CLK

I/O

TCP Port 3: Control Data

GPP_​D11 / ISH_​SPI_​MISO / DDP4_​CTRLCLK / TBT_​LSX3_​TXD / BSSB_​LS3_​RX / GSPI2_​MISO

I/O

TCP Port 4: Control Clock

GPP_​D12 / ISH_​SPI_​MOSI / DDP4_​CTRLDATA / TBT_​LSX3_​RXD / BSSB_​LS3_​TX / GSPI2_​MOSI

I/O

TCP Port 4: Control Data