| GPP_D0 / ISH_GP0 / BK0 / SBK0 | OD | Blink BK 0: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D1 / ISH_GP1 / BK1 / SBK1 | OD | Blink BK 1: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D2 / ISH_GP2 / BK2 / SBK2 | OD | Blink BK 2: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D3 / ISH_GP3 / BK3 / SBK3 | OD | Blink BK 3: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D4 / IMGCLKOUT0 / BK4 / SBK4 | OD | Blink BK 4: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_E22 / DDPA_CTRLCLK / DNX_FORCE_RELOAD | I | Download and Execute (DnX):Intel® CSME ROM samples this pin any time ROM begins execution. This includes the following conditions: - G3 Exit.
- Sx, Moff Exit.
- Cold Reset(Host Reset with Power Cycle) Exit.
- Warm Reset(Host Reset without Power Cycle) Exit if Intel® CSME was shutdown in Warm Reset.
- 0 => No DnX; 1 => Enter DnX mode.
This pin must not be sampled high at the sampling time for normal operation. |
| GPP_H12 / M2_SKT2_CFG0 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_H13 / M2_SKT2_CFG1 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_H14 / M2_SKT2_CFG2 (available in TGL PCH UP3 only) | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_H15 / M2_SKT2_CFG3 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_E0 / SATAXPCIE0 / SATAGP0 | I | SATA port 0 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_A12 / SATAXPCIE1 / SATAGP1 / I2S3_SFRM | I | SATA port 1 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express, M.2, or mSATA. |
| GPP_D0 / ISH_GP0 / BK0 / SBK0 | OD | Serial Blink SBK 0: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D1 / ISH_GP1 / BK1 / SBK1 | OD | Serial Blink SBK 1: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D2 / ISH_GP2 / BK2 / SBK2 | OD | Serial Blink SBK 2: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D3 / ISH_GP3 / BK3 / SBK3 | OD | Serial Blink SBK 3: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D4 / IMGCLKOUT0 / BK4 / SBK4 | OD | Serial Blink SBK 4: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_E19 / DDP1_CTRLDATA / TBT_LSX0_RXD / BSSB_LS0_TX | I/O | ThunderboltTM Low Speed Controller Receiver Data 0 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_E18 / DDP1_CTRLCLK / TBT_LSX0_TXD / BSSB_LS0_RX | I/O | Thunderbolt Low Speed Controller Transmit Data 0 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_E21 / DDP2_CTRLDATA / TBT_LSX1_RXD / BSSB_LS1_TX | I/O | Thunderbolt Low Speed Controller Receiver Data 1 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_E20 / DDP2_CTRLCLK / TBT_LSX1_TXD / BSSB_LS1_RX | I/O | Thunderbolt Low Speed Controller Transmit Data 1 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_D10 / ISH_SPI_CLK / DDP3_CTRLDATA / TBT_LSX2_RXD / BSSB_LS2_TX / GSPI2_CLK | I/O | Thunderbolt Low Speed Controller Receiver Data 2 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_D9 / ISH_SPI_CS# / DDP3_CTRLCLK / TBT_LSX2_TXD / BSSB_LS2_RX / GSPI2_CS0# | I/O | Thunderbolt Low Speed Controller Transmit Data 2 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_D12 / ISH_SPI_MOSI / DDP4_CTRLDATA / TBT_LSX3_RXD / BSSB_LS3_TX / GSPI2_MOSI | I/O | Thunderbolt Low Speed Controller Receiver Data 3 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_D11 / ISH_SPI_MISO / DDP4_CTRLCLK / TBT_LSX3_TXD / BSSB_LS3_RX / GSPI2_MISO | I/O | Thunderbolt Low Speed Controller Transmit Data 3 : The PCH LSx interface enables sideband communication for the Thunderbolt interface. |
| GPP_H23 / TIME_SYNC0 | I | Time Synchronization GPIO 0: Timed GPIO event for time synchronization for interfaces that do not support time synchronization natively. |
| GPP_B1 / GSPI1_CS1# / TIME_SYNC1 | I | Time Synchronization GPIO 1: Timed GPIO event for time synchronization for interfaces that do not support time synchronization natively. |