Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
Signal Description
PCH | Name | Type | Description |
---|---|---|---|
PCH-LP (UP3) | PCIE1_TXN / USB31_1_TXN PCIE1_TXP / USB31_1_TXP PCIE2_TXN / USB31_2_TXN PCIE2_TXP / USB31_2_TXP PCIE3_TXN / USB31_3_TXN PCIE3_TXP / USB31_3_TXP PCIE4_TXN / USB31_4_TXN PCIE4_TXP / USB31_4_TXP PCIE5_TXN PCIE5_TXP PCIE6_TXN PCIE6_TXP PCIE7_TXN PCIE7_TXP PCIE8_TXN PCIE8_TXP PCIE9_TXN PCIE9_TXP PCIE10_TXN PCIE10_TXP PCIE11_TXN / SATA0_TXN PCIE11_TXP / SATA0_TXP PCIE12_TXN / SATA1_TXN PCIE12_TXP / SATA1_TXP | O | PCI Express* Differential Transmit Pairs These are PCI Express* based outbound high-speed differential signals |
PCIE1_RXN / USB31_1_RXN PCIE1_RXP / USB31_1_RXP PCIE2_RXN / USB31_2_RXN PCIE2_RXP / USB31_2_RXP PCIE3_RXN / USB31_3_RXN PCIE3_RXP / USB31_3_RXP PCIE4_RXN / USB31_4_RXN PCIE4_RXP / USB31_4_RXP PCIE5_RXN PCIE5_RXP PCIE6_RXN PCIE6_RXP PCIE7_RXN PCIE7_RXP PCIE8_RXN PCIE8_RXP PCIE9_RXN PCIE9_RXP PCIE10_RXN PCIE10_RXP PCIE11_RXN / SATA0_RXN PCIE11_RXP / SATA0_RXP PCIE12_RXN / SATA1_RXN PCIE12_RXP / SATA1_RXP | I | PCI Express* Differential Receive Pairs These are PCI Express* based inbound high-speed differential signals | |
PCIE_RCOMP_P PCIE_RCOMP_N | I | Impedance Compensation Inputs | |
GPPC_H16 / PCIE_LINK_DOWN | O | PCIE_LINK_DOWN Output PCIe link failure debug signal. PCH PCIe Root Port(s) will assert this signal when a link down event occurs and is detected. For example when a link fails to train during an L1 sub-state exit event. | |
PCH-LP (UP4) | PCIE1_TXN / USB31_1_TXN PCIE1_TXP / USB31_1_TXP PCIE2_TXN / USB31_2_TXN PCIE2_TXP / USB31_2_TXP PCIE3_TXN / USB31_3_TXN PCIE3_TXP / USB31_3_TXP PCIE4_TXN / USB31_4_TXN PCIE4_TXP / USB31_4_TXP PCIE7_TXN PCIE7_TXP PCIE8_TXN PCIE8_TXP PCIE9_TXN PCIE9_TXP PCIE10_TXN PCIE10_TXP PCIE11_TXN PCIE11_TXP PCIE12_TXN PCIE12_TXP | O | PCI Express* Differential Transmit Pairs These are PCI Express* based outbound high-speed differential signals |
PCIE1_RXN / USB31_1_RXN PCIE1_RXP / USB31_1_RXP PCIE2_RXN / USB31_2_RXN PCIE2_RXP / USB31_2_RXP PCIE3_RXN / USB31_3_RXN PCIE3_RXP / USB31_3_RXP PCIE4_RXN / USB31_4_RXN PCIE4_RXP / USB31_4_RXP PCIE7_RXN PCIE7_RXP PCIE8_RXN PCIE8_RXP PCIE9_RXN PCIE9_RXP PCIE10_RXN PCIE10_RXP PCIE11_RXN PCIE11_RXP PCIE12_RXN PCIE12_RXP | I | PCI Express* Differential Receive Pairs These are PCI Express* based inbound high-speed differential signals | |
PCIE_RCOMP_N PCIE_RCOMP_P | I | Impedance Compensation Inputs | |
GPPC_H16 / PCIE_LINK_DOWN | O | PCIE_LINK_DOWN Output PCIe link failure debug signal. PCH PCIe Root Port(s) will assert this signal when a link down event occurs and is detected. For example when a link fails to train during an L1 sub-state exit event. |