Sleep State Overview

The PCH supports different sleep states (S4/S5), which are entered by methods such as setting the SLP_​EN bit or due to a Power Button press. The entry to the Sleep states is based on several assumptions:

• The G3 state cannot be entered using any software mechanism. The G3 state indicates a complete loss of power.

Initiating Sleep State

Sleep states (S4/S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_​TYP field, and then setting the SLP_​EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies from the processor or on clocks other than the RTC clock.
• Assertion of the THERMTRIP# signal will cause a transition to the S5 state. This can occur when system is in the S0 state.
• Shutdown by integrated manageability functions (ASF/Intel CSME).
• Internal watchdog timer timeout events.

Exiting Sleep States

Sleep states (S4/S5) are exited based on wake events. The wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the storage subsystem may be shut off during a sleep state and have to be enabled using a GPIO pin before it can be used.

Upon exit from the PCH-controlled Sleep states, the WAK_​STS bit is set. The possible causes of wake events (and their restrictions) are shown in the table below.

PCI Express* WAKE# Signal and PME Event Message

PCI Express* ports can wake the platform from S4, S5, or Deep Sx using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_​STS register.

PCI Express* ports and the processor have the ability to cause PME using messages.These are logically OR’d to set the single PCI_​EXP_​STS bit. When a PME message is received, the PCH will set the PCI_​EXP_​STS bit. If the PCI_​EXP_​EN bit is also set, the PCH can cause an SCI via GPE0_​STS register.

Sx-G3-Sx, Handling Power Failures

Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure.

The AFTERG3_​EN bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When PCH_​DPWROK is low (G3 state), the PWRBTN_​STS bit is reset. When the PCH exits G3 after power returns (PCH_​DPWROK goes high), the PWRBTN# signal will transition high due internal Pull-up, unless there is an on-board Pull-up/Pull-down) and the PWRBTN_​STS bit is 0.
2. RTC Alarm: The RTC_​EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_​STS the RTC_​STS bit is cleared when PCH_​DPWROK goes low.
3. Any enabled wake event that was preserved through the power failure.

DSW_​PWROK going low would place the PCH into a G3 state.

Although PME_​EN is in the RTC well, this signal cannot wake the system after a power loss. PME_​EN is cleared by RTCRST#, and PME_​STS is cleared by RSMRST#.

Deep Sx

To minimize power consumption while in S4/S5, the PCH supports a lower power, lower featured version of these power states known as Deep Sx. In the Deep Sx state, the primary wells are powered off, while the Deep Sx Well (DSW) remains powered. A limited set of wake events are supported by the logic located in the DSW.

The Deep Sx capability and the SUSPWRDNACK pin functionality are mutually exclusive.

• Entry Into Deep Sx

A combination of conditions is required for entry into Deep Sx. PMC firmware is responsible for enforcing these requirements. The requirements, all of which must be met to enter Deep Sx, are detailed below :

• RTCPMCFG.INT_​SUS_​PD_​EN = 1
  • Intel CSME must program this bit prior to initiating CMOFF or CM3-PG entry
• Intel CSME in CMOFF or CM3-PG
  • Deep Sx conditions are checked during CMOFF and CM3-PG entry.  If Deep Sx entry would have been allowed if the ACPRESENT# signal had been high, PMC FW will enable ACPRESENT# as an interrupt source, initiating Deep Sx entry if the power source changes to match the required state
• Host in S4, or S5 and combination of S-state and power source matches the host policy bits
  • ( (S4AC_​GATE_​SUS AND S4) OR

OR

• ((ACPRESENT = 0) AND ( (S4DC_​GATE_​SUS AND S4) OR (S5DC_​GATE_​SUS AND S5)))

• Either Deep Sx entry is not determined by BATLOW# state or BATLOW# is asserted
  • REQ_​BATLOW_​DSX == ‘0’ OR BATLOW# == ‘0’
• Either Deep Sx entry is not determined by connectivity wake enable or connectivity wake is enabled
  • REQ_​CNV_​NOWAKE_​DSX == ‘0’ OR SLP_​WLAN_​VAL == ‘0’

The PCH also performs a SUSWARN#/SUSACK# handshake to ensure the platform is ready to enter Deep Sx. The PCH asserts SUSWARN# as notification that it is about to enter Deep Sx. Before the PCH proceeds and asserts SLP_​SUS#, the PCH waits for SUSACK# to assert.

• Exit from Deep Sx

While in Deep Sx, the PCH monitors and responds to a limited set of wake events (RTC Alarm, Power Button and WAKE#). Upon sensing an enabled Deep Sx wake event, the PCH brings up the primary well by de-asserting SLP_​SUS#.

ACPRESENT has some behaviors that are different from the other Deep Sx wake events. If the Intel CSME has enabled ACPRESENT as a wake event then it behaves just like any other Intel CSME Deep Sx wake event. However, even if ACPRESENT wakes are not enabled, if the Host policies indicate that Deep Sx is only supported when on battery, then ACPRESENT going high will cause the PCH to exit Deep Sx. In this case, the primary wells gets powered up and the platform remains in Sx/M-Off or Sx/M3-PGS3/M-Off. If ACPRESENT subsequently drops (before any Host or Intel^® CSME wake events are detected), the PCH will re-enter Deep Sx.