SMBus Slave Interface
The PCH SMBus Slave interface is accessed using the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the PCH to decode cycles, and allows an external micro controller to perform specific actions.
Key features and capabilities include:
- Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify.
- Receive Slave Address register: This is the address that the PCH decodes. A default value is provided so that the slave interface can be used without the processor having to program this register.
- Receive Slave Data register in the SMBus I/O space that includes the data written by the external micro controller.
- Registers that the external micro controller can read to get the state of the PCH.
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more in the middle of a cycle, the PCH slave logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic.
Format of Slave Write Cycle
The external master performs Byte Write commands to the PCH SMBus Slave I/F. The “Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register.
The table below has the values associated with the registers.
Format of Read Command
The external master performs Byte Read commands to the PCH SMBus Slave interface. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register.
| Bit | Description | Driven By | Comment |
|---|---|---|---|
| 1 | Start | External Micro controller | |
| 2–8 | Slave Address - 7 bits | External Micro controller | Must match value in Receive Slave Address register |
| 9 | Write | External Micro controller | Always 0 |
| 10 | ACK | PCH | |
| 11–18 | Command code – 8 bits | External Micro controller | Indicates which register is being accessed. Refer to the Table below for a list of implemented registers. |
| 19 | ACK | PCH | |
| 20 | Repeated Start | External Micro controller | |
| 21–27 | Slave Address - 7 bits | External Micro controller | Must match value in Receive Slave Address register |
| 28 | Read | External Micro controller | Always 1 |
| 29 | ACK | PCH | |
| 30–37 | Data Byte | PCH | Value depends on register being accessed. Refer to the Table below for a list of implemented registers. |
| 38 | NOT ACK | External Micro controller | |
| 39 | Stop | External Micro controller |
- Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit—Address—Write bit sequence. When the PCH detects that the address matches the value in the Receive Slave Address register, it will assume that the protocol is always followed and ignore the Write bit (Bit 9) and signal an Acknowledge during bit 10. In other words, if a Start—Address—Read occurs (which is invalid for SMBus Read or Write protocol), and the address matches the PCH’s Slave Address, the PCH will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start—Address—Read sequence beginning at Bit 20. Once again, if the Address matches the PCH’s Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle.
Slave Read of RTC Time Bytes
The PCH SMBus slave interface allows external SMBus master to read the internal RTC’s time byte registers.
The RTC time bytes are internally latched by the PCH’s hardware whenever RTC time is not changing and SMBus is idle. This ensures that the time byte delivered to the slave read is always valid and it does not change when the read is still in progress on the bus. The RTC time will change whenever hardware update is in progress, or there is a software write to the RTC time bytes.
The PCH SMBus slave interface only supports Byte Read operation. The external SMBus master will read the RTC time bytes one after another. It is the software’s responsibility to check and manage the possible time rollover when subsequent time bytes are read.
For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the external SMBus master reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. This results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless it is certain that rollover will not occur, software is required to detect the possible time rollover by reading multiple times such that the read time bytes can be adjusted accordingly if needed.
Format of Host Notify Command
The PCH tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the PCH already has data for a previously - received host notify command which has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non - acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt.
The table below shows the Host Notify format:
| Bit | Description | Driven By | Comment |
|---|---|---|---|
| 1 | Start | External Master | |
| 8:2 | SMB Host Address – 7 bits | External Master | Always 0001_000 |
| 9 | Write | External Master | Always 0 |
| 10 | ACK (or NACK) | PCH | PCH NACKs if HOST_NOTIFY_STS is 1 |
| 17:11 | Device Address – 7 bits | External Master | Indicates the address of the master; loaded into the Notify Device Address Register |
| 18 | Unused – Always 0 | External Master | 7 - bit - only address; this bit is inserted to complete the byte |
| 19 | ACK | PCH | |
| 27:20 | Data Byte Low – 8 bits | External Master | Loaded into the Notify Data Low Byte Register |
| 28 | ACK | PCH | |
| 36:29 | Data Byte High – 8 bits | External Master | Loaded into the Notify Data High Byte Register |
| 37 | ACK | PCH | |
| 38 | Stop | External Master |
Format of Read Command
The external master performs Byte Read commands to the PCH SMBus Slave interface. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register.
| Bit | Description | Driven By | Comment |
|---|---|---|---|
| 1 | Start | External Micro controller | |
| 2–8 | Slave Address - 7 bits | External Micro controller | Must match value in Receive Slave Address register |
| 9 | Write | External Micro controller | Always 0 |
| 10 | ACK | PCH | |
| 11–18 | Command code – 8 bits | External Micro controller | Indicates which register is being accessed. Refer to the Table below for a list of implemented registers. |
| 19 | ACK | PCH | |
| 20 | Repeated Start | External Micro controller | |
| 21–27 | Slave Address - 7 bits | External Micro controller | Must match value in Receive Slave Address register |
| 28 | Read | External Micro controller | Always 1 |
| 29 | ACK | PCH | |
| 30–37 | Data Byte | PCH | Value depends on register being accessed. Refer to the Table below for a list of implemented registers. |
| 38 | NOT ACK | External Micro controller | |
| 39 | Stop | External Micro controller |
| Event | INTREN (Host Control I/O Register, Offset 02h, Bit 0) | SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) | Event |
|---|---|---|---|
| Slave Write to Wake/SMI# Command | X | X | Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS) |
| Slave Write to SMLINK_SLAVE_SMI Command | X | X | Slave SMI# generated when in the S0 state (SMBUS_SMI_STS) |
| Any combination of Host Status Register [4:1] asserted | 0 | X | None |
| 1 | 0 | Interrupt generated | |
| 1 | 1 | Host SMI# generated |