SMI#/SCI Generation
Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, the PCH will clear the EOS bit and assert SMI to the processor, which will cause it to enter SMM space. SMI assertion is performed using a Virtual Legacy Wire (VLW) message.
Once the SMI VLW has been delivered, the PCH takes no action on behalf of active SMI events until Host software sets the End of SMI (EOS) bit. At that point, if any SMI events are still active, the PCH will send another SMI VLW message.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not. The interrupt remains asserted until all SCI sources are removed.
The table below shows which events can cause an SMI and SCI.
| Cause | SCI | SMI | Additional Enables 1 | Where Reported |
|---|---|---|---|---|
| PME# | Yes | Yes | PME_EN=1 | PME_STS |
| PME_B0 (Internal, Bus 0, PME-Capable Agents) | Yes | Yes | PME_B0_EN=1 | PME_B0_STS |
| PCI Express* PME Messages | Yes | Yes | PCI_EXP_EN=1 (Not enabled for SMI) | PCI_EXP_STS |
| PCI Express* Hot-Plug Message | Yes | Yes | HOT_PLUG_EN=1 (Not enabled for SMI) | HOT_PLUG_STS |
| Power Button Press | Yes | Yes | PWRBTN_EN=1 | PWRBTN_STS |
| Power Button Override (Note 6) | Yes | No | None | PWRBTNOR_STS |
| RTC Alarm | Yes | Yes | RTC_EN=1 | RTC_STS |
| ACPI Timer overflow (2.34 seconds) | Yes | Yes | TMROF_EN=1 | TMROF_STS |
| GPIO | Yes | Yes | Refer to Note 8 | |
| LAN_WAKE# | Yes | Yes | SCI_EN=0, LAN_WAKE_EN=1 | LAN_WAKE_STS |
| TCO SCI message from processor | Yes | No | None | CPUSCI_STS |
| TCO SCI Logic | Yes | No | TCOSCI_EN=1 | TCOSCI_STS |
| TCO SMI Logic | No | Yes | TCO_EN=1 | TCO_STS |
| TCO SMI – Year 2000 Rollover | No | Yes | None | NEWCENTURY_STS |
| TCO SMI – TCO TIMEROUT | No | Yes | None | TIMEOUT |
| TCO SMI – OS writes to TCO_DAT_IN register | No | Yes | None | OS_TCO_SMI |
| TCO SMI – NMI occurred (and NMIs mapped to SMI) | No | Yes | NMI2SMI_EN=1 | TCO_STS, NMI2SMI_STS |
| TCO SMI – INTRUDER# signal goes active | No | Yes | INTRD_SEL=10 | INTRD_DET |
| TCO SMI – Changes of the WPD (Write Protect Disable) bit from 0 to 1 | No | Yes | LE (Lock Enable)=1 | BIOSWR_STS |
| TCO SMI – Write attempted to BIOS | No | Yes | WPD=0 | BIOSWR_STS |
| BIOS_RLS written to 1 (Note 7) | Yes | No | GBL_EN=1 | GBL_STS |
| GBL_RLS written to | No | Yes | BIOS_EN=1 | BIOS_STS |
| Write to B2h register | No | Yes | APMC_EN = 1 | APM_STS |
| Periodic timer expires | No | Yes | PERIODIC_EN=1 | PERIODIC_STS |
| 64 ms timer expires | No | Yes | SWSMI_TMR_EN=1 | SWSMI_TMR_STS |
| Enhanced USB Legacy Support Event | No | Yes | LEGACY_USB2_EN = 1 | LEGACY_USB2_STS |
| Serial IRQ SMI reported | No | Yes | None | SERIRQ_SMI_STS |
| Device monitors match address in its range | No | Yes | Refer to DEVTRAP_STS register description | DEVTRAP_STS |
| SMBus Host Controller | No | Yes | SMB_SMI_EN, Host Controller Enabled | SMBus host status reg. |
| SMBus Slave SMI message | No | Yes | None | SMBUS_SMI_STS |
| SMBus SMBALERT# signal active | No | Yes | None | SMBUS_SMI_STS |
| SMBus Host Notify message received | No | Yes | HOST_NOTIFY_INTREN | SMBUS_SMI_STS, HOST_NOTIFY_STS |
| BATLOW# assertion | Yes | Yes | BATLOW_EN=1 | BATLOW_STS |
| Access microcontroller 62h/66h | No | Yes | MCSMI_EN | MCSMI_STS |
| SLP_EN bit written to 1 | No | Yes | SMI_ON_SLP_EN=1 | SMI_ON_SLP_EN_STS |
| SPI Command Completed | No | Yes | None | SPI_SMI_STS |
| eSPI SCI/SMI Request 9 | Yes | Yes | eSPI_SCI_EN | eSPI_SCI_STS eSPI_SMI_STS |
| Software Generated GPE | Yes | Yes | SWGPE_EN=1 | SWGPE_STS |
| Intel® CSME | Yes | Yes | CSME_SCI_EN=1 CSME_SCI_EN=0; CSME_SMI_EN=1; | CSME_SCI_STS CSME_SMI_STS |
| GPIO Lockdown Enable bit changes from ‘1’ to ‘0’ | No | Yes | GPIO_UNLOCK_SMI_EN=1 | GPIO_UNLOCK_SMI_STS |
| USB 3.2 (xHCI) SMI Event | No | Yes | xHCI_SMI_EN=1 | xHCI_SMI_STS |
| Wake Alarm Device Timer | Yes | Yes | WADT_EN | WADT_STS |
| ISH | Yes | No | ISH_EN | ISH_STS |
| RTC update-in-progress | No | Yes | Refer to Vol2 as reference | RTC_UIP_SMI_STS |
| SIO SMI events | No | Yes | SIP_SMI_EN | SIO_SMI_STS |
| SCC | No | Yes | SCC_SMI_EN | SCC_SMI_STS |
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PCI Express* SCI
PCI Express* ports and the processor have the ability to cause PME using messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the PCH can cause an SCI using the GPE0_STS (replaced GPE1_STS) register.
PCI Express* Hot-Plug
PCI Express* has a hot-plug mechanism and is capable of generating a SCI using the GPE0 (replaced GPE1) register. It is also capable of generating an SMI. However, it is not capable of generating a wake event.