System Power Supplies, Planes, and Signals
Power Plane Control
The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power must be maintained to the PCH primary well, and to any other circuits that need to generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM) all signals attached to powered down planes will be tri-stated or driven low, unless they are pulled using a Pull-up resistor.
Cutting power to the system core supply may be done using the power supply or by external FETs on the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard.
SLP_S5# output signal can be used to cut power to the system core supply.
SLP_A# output signal can be used to cut power to the Intel® Converged Security and Management Engine and SPI flash on a platform that supports the M3 state (for example, certain power policies in Intel® AMT).
SLP_LAN# output signal can be used to cut power to the external Intel GbE PHY device.
SLP_S4# and Suspend-to-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time.
PCH_PWROK Signal
When asserted, PCH_PWROK is an indication to the PCH that its core well power rails are powered and stable. PCH_PWROK can be driven asynchronously. When PCH_PWROK is low, the PCH asynchronously asserts PLTRST#. PCH_PWROK must not glitch, even if RSMRST# is low.
It is required that the power associated with PCIe* have been valid for 99 ms prior to PCH_PWROK assertion in order to comply with the 100 ms PCIe* 2.0 specification on PLTRST# de-assertion.
BATLOW# (Battery Low)
The BATLOW# input can inhibit waking from S3, S4, S5 and Deep Sx states if there is not sufficient power. It also causes an SMI if the system is already in an S0 state.
SLP_LAN# Pin Behavior
The PCH controls the voltage rails into the external LAN PHY using the SLP_LAN# pin.
- The LAN PHY is always powered when the Host and Intel® CSME systems are running.
- If the LAN PHY is required by Intel® CSME in Sx/M-Off or Deep Sx, Intel® CSME must configure SLP_LAN#=’1’ irrespective of the power source and the destination power state. Intel® CSME must be powered at least once after G3 to configure this.
- If the LAN PHY is required after a G3 transition, the host BIOS must set AG3_PP_EN.
- If the LAN PHY is required in Sx/M-Off, the host BIOS must set SX_PP_EN.
- If the LAN PHY is required in Deep Sx, the host BIOS must keep DSX_PP_DIS cleared.
- If the LAN PHY is not required if the source of power is battery, the host BIOS must set DC_PP_DIS.
The flow chart below shows how a decision is made to drive SLP_LAN# every time its policy needs to be evaluated.
Conceptual Diagram of SLP_LAN#
SLP_WLAN# Pin Behavior
The PCH controls the voltage rails into the external wireless LAN PHY using the SLP_WLAN# pin.
- The wireless LAN PHY is always powered when the Host is running.
- If Wake on Wireless LAN (WoWLAN) is required from S3/S4/S5 states, the host BIOS must set HOST_WLAN_PP_EN.
- If WoWLAN is required from Deep Sx, the host BIOS must set DSX_WLAN_PP_EN.
- If Intel® CSME has access to the Wireless LAN device:
Intel® CSME configuration of SLP_WLAN# in Sx/M-Off is dependent on Intel® CSME power policy configuration.
When the Wireless LAN device is an integrated connectivity device (CNVi) the power to the CNVi external RF chip (CRF) must be always on. In this case the SLP_WLAN# shall not control the CRF 3.3 V power rail.
EXT_PWR_GATE# Pin Behavior
EXT_PWR_GATE# can be used to control a FET gating off the HSIO/SRAM power supply to PCH. This provides additional power savings during connected standby states. The ramp time of the FET can be controlled via MODPHY_PM_CFG3.
It is expected that the HSIO/SRAM supply will ramp along with the other primary wells, and must be valid for at least 10 ms before RSMRST# deassertion during a G3/Deep Sx -> Sx transition. System designers will need to account for this behavior to make sure the rail turns on as expected.
SUSPWRDNACK/SUSWARN#/GPP_A13 Steady State Pin Behavior
Below table summarizes SUSPWRDNACK/SUSWARN#/GPP_A13 pin behavior.
| Reset Type (Note) | SPDA Value |
|---|---|
| Power-cycle Reset | 0 |
| Global Reset | 0 |
| Straight to S5 | PCH initially drive ‘0’ and then drive per Intel® CSME power policy configuration. |
| | |
RTCRST# and SRTCRST#
RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a jumper is used on this pin, it should only be pulled low when system is in the G3 state and then replaced to the default jumper position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear internal PCH registers accordingly. It is imperative that this signal not be pulled low in the S0 to S5 states.
SRTCRST# is used to reset portions of the Intel® Converged Security and Management Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that SRTCRST# not be pulled low in the S0 to S5 states.