Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

Variable I/O Decode Ranges

The following table shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various configuration spaces. The PnP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values.

Warning:The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. There may some unpredictable results if the configuration software allows conflicts to occur. The PCH does not perform any checks for conflicts.

Variable I/O Decode Ranges 

Range Name1

Mappable

Size (Bytes)

Target

ACPI

Anywhere in 64K I/O Space

256

Power Management

IDE Bus Master

Anywhere in 64K I/O Space

16 or 32 Bytes

Intel® AMT IDE-R

SMBus

Anywhere in 64K I/O Space

32

SMB Unit

TCO

Anywhere in 64K I/O Space

32

SMB Unit

Parallel Port

3 ranges in 64K I/O Space

8

eSPI

Serial Port 1

8 Ranges in 64K I/O Space

8

eSPI

Serial Port 2

8 Ranges in 64K I/O Space

8

eSPI

Serial Port 3

8 Ranges in 64K I/O space

8

eSPI

Floppy Disk Controller

2 Ranges in 64K I/O Space

8

eSPI

IO Trapping Ranges

Anywhere in 64K I/O Space

1 to 256 Bytes

Trap

Serial ATA Index/Data Pair

Anywhere in 64K I/O Space

16

SATA Host Controller

PCI Express* Root Ports

Anywhere in 64K I/O Space

I/O Base/Limit

PCI Express Root Ports 1-24

Keyboard and Text (KT)

Anywhere in 64K I/O Space

8

Intel® AMT Keyboard and Text

Note:1. All ranges are decoded directly from OPI.