Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

Display Interfaces

Display DDI Data and Clock Signals

Package Pin

Dir.

eDP

MIPI DSI

DP

HDMI

DISP_​RCOMP

N/A

Common RCOMP for all PHYs

DDI0_​AUXP

DDI0_​AUXN

I/O

eDP Auxiliary Channel (AUX_​CH)

MIPI0 Data 0

DP0 Auxiliary Channel (AUX_​CH)

NC

DDI0_​TXN0

DDI0_​TXP0

I/O

eDP Main Link,

Lane 0 (ML_​Lane 0)

MIPI0 Data 1

DP0 Main Link,

Lane 0 (ML_​Lane 0)

TMDS0 Data2

DDI0_​TXN1

DDI0_​TXP1

O

eDP Main Link,

Lane 1 (ML_​Lane 1)

MIPI0 Data 2

DP0 Main Link,

Lane 1 (ML_​Lane 1)

TMDS0 Data1

DDI0_​TXN2

DDI0_​TXP2

O

eDP Main Link,

Lane 2 (ML_​Lane 2)

MIPI0 Clock

DP0 Main Link,

Lane 2 (ML_​Lane 2)

TMDS0 Data 0

DDI0_​TXN3

DDI0_​TXP3

O

eDP Main Link,

Lane 3 (ML_​Lane 3)

MIPI0 Data 3

DP0 Main Link,

Lane 3 (ML_​Lane 3)

TMDS0 Clock

DDI1_​AUXN

DDI1_​AUXP

I/O

NC

MIPI1 Data 0

DP1 Auxiliary Channel (AUX_​CH)

NC

DDI1_​TXN0

DDI1_​TXP0

I/O

NC

MIPI1 Data 1

DP1 Main Link,

Lane 0 (ML_​Lane 0)

TMDS1 Data2

DDI1_​TXN1

DDI1_​TXP1

O

NC

MIPI1 Data 2

DP1 Main Link,

Lane 1 (ML_​Lane 1)

TMDS1 Data1

DDI1_​TXN2

DDI1_​TXP2

O

NC

MIPI1 Clock

DP1 Main Link,

Lane 2 (ML_​Lane 2)

TMDS1 Data0

DDI1_​TXN3

DDI1_​TXP3

O

NC

MIPI1 Data 3

DP1 Main Link,

Lane 3 (ML_​Lane 3)

TMDS1 Clock

DDI2_​AUXN

DDI2_​AUXP

I/O

NC

NC

DP2 Auxiliary Channel (AUX_​CH)

NC

DDI2_​TXN0

DDI2_​TXP0

I/O

NC

NC

DP2 Main Link,

Lane 0 (ML_​Lane 0)

TMDS2 Data2

DDI2_​TXN1

DDI2_​TXP1

O

NC

NC

DP2 Main Link,

Lane 1 (ML_​Lane 1)

TMDS2 Data1

DDI2_​TXN2

DDI2_​TXP2

O

NC

NC

DP2 Main Link,

Lane 2 (ML_​Lane 2)

TMDS2 Data0

DDI2_​TXN3

DDI2_​TXP3

O

NC

NC

DP2 Main Link,

Lane 3 (ML_​Lane 3)

TMDS2 Clock

Pin Mapping for Display Control Signals

Display Signals

Dir.

Description

Usage Model

eDP/DP/HDMI Port 0, DP/HDMI Port 1,

DP/HDMI Port 2

DSI Dual Link Port 0+1,

DP/HDMI Port 2

DSI Port 0,

DP/HDMI port 1,

DP/HDMI Port 2(Note1)

DSI Port 0,

DP/HDMI Port 2 (Note2)

DDI0_​HPD

I/O

DDI0 Hot Plug Detection

DDI0 eDP HPD

DDI1_​HPD

I/O

DDI1 Hot Plug Detection

DP/HDMI HPD

DDI1 DP/HDMI HPD

eDP_​VDDEN

I/O

Panel main power enable

VDD enable for eDP

MIPI DSI power enable AVDD

MIPI DSIPower

Enable AVDD

MIPI DSI Power

Enable AVDD

DDI2_​HPD

I

Dedicated DDI2 Hot Plug Detection

DDI2 DP/HDMI HPD

DDI2 DP/HDMI HPD

DDI2 DP/HDMI HPD

DDI2 DP/HDMI HPD

eDP_​BKLTEN

O

Panel backlight enable

eDP Backlight Enable

MIPI DSI Backlight Enable

MIPI DSI Backlight Enable

MIPI DSI Backlight Enable

eDP_​BKLTCTL

O

Panel backlight control

eDP Backlight Control

MIPI DSI

Backlight Control

MIPI DSI Backlight Control

MIPI DSI Backlight Control

DDI0_​DDC_​SCL

I/O

Panel reset or DDC clock for HDMI 0 or DSI panel secondary power (AVEE)

Control Clock 0

DSI power AVEE

MIPI0 Reset

DSI power AVEE

DDI0_​DDC_​SDA

I/O

DDC data for HDMI 0 or DSI panel secondary power (AVDD)

Control Data 0

DSI power AVDD

DSI power AVEE

DSI power AVEE

DDI1_​DDC_​SCL

I/O

Panel reset or DDC clock for HDMI 1

Control Clock 1

Dual Link Mode Reset

Control Clock 1

MIPI0 Reset

DDI1_​DDC_​SDA

I/O

DDC data for HDMI 1

Control Data 1

Control Data 1

DDI2_​DDC_​SCL

I/O

Dedicated DDI2 DDC

Clock for HDMI or DP++

Control Clock 2

Control Clock 2

Control Clock 2

Control Clock 2

DDI2_​DDC_​SDA

I/O

Dedicated DDI2 DDC

Data for HDMI and DP++

Control Data 2

Control Data 2

Control Data 2

DDI2 DDC Data

MDSI_​DE_​TE_​1

I/O

Tearing Effect from MIPI Panel 0

Dual link MIPI TE

MIPI0 TE

MIPI0 TE

MDSI_​DE_​TE_​2

I/O

Tearing Effect from MIPI Panel 1

Dual link MIPI TE

Notes:

  1. Usage that supports DP/HDMI port 1. Cannot support dual independent DSI analog/secondary power controls.
  2. Usage that supports dual independent DSI analog/secondary power controls. Cannot support DP/HDMI port 1
  3. MIPI Reset is not validated on Intel RVP
  4. PNL_​VDDEN, PNL_​BLKLTEN, PNL_​BKLTCTL can be left no connect if neither eDP or MIPI-DSI is not used.