Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

DRAM Channel Support Matrix and Signals Terminology

LPDDR4x Sub-Channels Population Rules

Number of DRAMs

DRAM Type

Sub-Channel Population

2

x32

DRAM 0 is connected to Sub Channel A

DRAM 1 is connected to Sub Channel B

4

x32

DRAM 0 is connected to Sub Channel A

DRAM 1 is connected to Sub Channel B

DRAM 2 is connected to Sub Channel C

DRAM 3 is connected to Sub Channel D

System Memory Interface Signals Terminology

Memory Type

DDR4

SoDIMM

(Per Channel)

LPDDR4/4x

Memory Down

(All Channels)

Signal details

Clock (CLK)

DDR_​[1:0]_​CLK[1:0]_​DN, DDR_​[1:0]_​CLK[1:0]_​DP

LP4x_​[3:0]_​CLK_​DN,

LP4x_​[3:0]_​CLK_​DP

Control (CTRL)

DDR_​[1:0]_​CS[1:0]_​N,

DDR_​[1:0]_​ODT[1:0]

LP4x_​0_​CS0

LP4x_​1_​CS1

LP4x_​2_​CS0

LP4x_​3_​CS1

Clock Enable (CKE)

DDR_​[1:0]_​CKE[1:0]

LP4x_​0_​CKE0

LP4x_​1_​CKE1

LP4x_​2_​CKE0

LP4x_​3_​CKE1

Command (CMD)

DDR_​[1:0]_​MA[13:0],

DDR_​[1:0]_​MA14_​WE_​N,

DDR_​[1:0]_​MA15_​CAS_​N,

DDR_​[1:0]_​MA16_​RAS_​N,

DDR_​[1:0]_​BG[1:0],

DDR_​[1:0]_​BA[1:0],

DDR_​[1:0]_​ACT_​N,

DDR_​[1:0]_​PAR

LP4x_​[3:0]_​CA[5:0]

Alert

DDR_​[1:0]_​ALERT_​N

N/A

Strobe

DDR_​[1:0]_​DQS[7:0]_​DN,

DDR_​[1:0]_​DQS[7:0]_​DP

LP4x_​[3:0]_​DQS[3:0]_​DN,

LP4x_​[3:0]_​DQS[3:0]_​DP

Data

DDR_​[1:0]_​DQ[63:0]

LP4x_​[3:0]_​DQ[31:0]

Reset

PMC_​DRAM_​RESET_​N

PMC_​DRAM_​RESET_​N

RCOMP

DDR_​RCOMP[2:0]

LP4x_​RCOMP[2:0]

Vref

DDR_​[1:0]_​VREF_​CA

N/A

VTT

DDR_​VTT_​CTL

N/A

SA Speed Enhanced Speed Steps (SA-GV) and Gear Mode Frequencies

DDR max rate

[MT/s]

SAGV-Low

DDR CLK, Gear

SAGV-Mid

DDR CLK, Gear

SAGV-High

DDR CLK, Gear

DDR4 2133 2133,G2 2133,G2 2133,G2
2400 2133,G2 2400,G2 2400,G2
2666 2133,G2 2400,G2 2666,G2
2933 2133,G2 2400,G2 2933,G2
LPDDR4/x 2133 2133,G2 2133,G2 2133,G2
2400 2133,G2 2400,G2 2400,G2
2666 2133,G2 2400,G2 2666,G2
2933 2133,G2 2400,G2 2933,G2
Notes:
  1. Intel® Pentium® Silver and Intel® Celeron® Processor supports dynamic gearing technology where the Memory Controller can run at 1:2 (Gear-2 mode)ratio of DRAM speed. Gear ratio is the ratio of DRAM speed to Memory Controller Clock.

    MC Channel Width equal to DDR Channel width multiply by Gear Ratio.

  2. SA-GV modes:
    1. Low- Low frequency point, Min Power point. Characterized by low power, low BW, high latency. System will stay at this point during low to moderate BW consumption.

    2. Mid - Max Bandwidths Point, this point is the max possible BW point, the DRAM freq limited by Silicon Configuration/BIOS/SPD. Characterized by moderate power and latency, high BW. This point intended for high GT and moderate-high IA BW

    3. High - High Point, the minimum memory latency point, Characterized by high power, low latency, moderate BW. Only during IA performance workloads the system will to switch to this point and only in case this point can provide enough BW.