Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

General DC Characteristics

Single-Ended Signal DC Characteristics as Inputs or Outputs

Type

Symbol

Parameter

Minimum

Maximum

Unit

Condition

Notes

Notes:
  1. For GPIO supported voltages, refer to General Purpose Input and Output (GPIO).
  2. Maximum overshoot voltage is 2.19 V
  3. Min undershoot voltage is -0.28
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.

Associated Signals1: GP_​G00/SD_​SDIO_​CMD, GP_​G01/SD_​SDIO_​D0, GP_​G02/SD_​SDIO_​D1, GP_​G03/SD_​SDIO_​D2, GP_​G04/SD_​SDIO_​D3, GP_​G05/SD_​SDIO_​CD_​N, GP_​G06/SD_​SDIO_​CLK, GP_​G07/SD_​SDIO_​WP

3.3 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-14

14

µA

CIN

Input Pin Capacitance

14

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

Only for 50 ohm mode

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Only for 50 ohm mode

Rpu

WPU 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.3 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.7 * VCC

1.8 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-14

14

µA

CIN

Input Pin Capacitance

14

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

Only for 50 ohm mode

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Only for 50 ohm mode

Rpu

WPU 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.3 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.7 * VCC

Notes:
  1. For GPIO supported voltages, refer to General Purpose Input and Output (GPIO)
  2. If GP_​G[00:07] are used for SD functionality, pins are dynamically configured based on SD card capability otherwise if used as GPIO it can be configured to 3.3V or 1.8V.
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.
Associated Signals1: GP_​DSW09/PMC_​SLP_​WLAN_​N, GP_​DSW08/PMC_​SUSCLK, GP_​DSW07, GP_​DSW06/PMC_​SLP_​A_​N, GP_​DSW05/PMC_​SLP_​S4_​N, GP_​DSW04/PMC_​SLP_​S3_​N, GP_​DSW03/PMC_​PWRBTN_​N, GP_​DSW02/LAN_​WAKE_​N, GP_​DSW10/PMC_​SLP_​S5_​N, GP_​DSW01/PMC_​ACPRESENT, GP_​DSW00/PMC_​BATLOW_​N, PMC_​SLP_​SUS_​N, PMC_​WAKE_​N, PMC_​DRAM_​RESET_​N

3.3 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-10

10

µA

CIN

Input Pin Capacitance

14

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Rpu

WPU 5K/20K Resistance

1K-50%

5K-70%

20K-35%

1K+100%

5K+70%

20K+35%

Ohm

0.7 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-35%

5K+70%

20K+35%

Ohm

0.3 * VCC

Note:For GPIO supported voltages, refer to General Purpose Input and Output (GPIO).
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.

Associated Signals1: GP_​B09/PCIE_​CLKREQ4_​N, GP_​B08/PCIE_​CLKREQ3_​N, GP_​B07/PCIE_​CLKREQ2_​N, GP_​B06/PCIE_​CLKREQ1_​N, GP_​B05/PCIE_​CLKREQ0_​N, GP_​B04/CPU_​GP_​3, GP_​B03/CPU_​GP_​2, GP_​B23/DDI2_​HPD/TIME_​SYNC_​0/GSPI1_​CS1_​N, GP_​B22/GSPI1_​MOSI, GP_​B21/GSPI1_​MISO/NFC_​CLKREQ, GP_​B20/GSPI1_​CLK/NFC_​CLK, GP_​B02/PMC_​VRALERT_​N, GP_​B19/GSPI1_​CS0_​N, GP_​B18/GSPI0_​MOSI/UART2A_​TXD, GP_​B17/GSPI0_​MISO/UART2A_​RXD, GP_​B16/GSPI0_​CLK, GP_​B15/GSPI0_​CS0_​N, GP_​B14/SPKR_​GSPI0_​CS1_​N, GP_​B13/PMC_​PLTRST_​N, GP_​B12/PMC_​SLP_​S0_​N, GP_​B11/PMCALERT_​N, GP_​B10/PCIE_​CLKREQ5_​N, GP_​B01/PMC_​CORE_​VID1, GP_​B00/PMC_​CORE_​VID0, GP_​H09/I2C4_​SCL, GP_​H08/I2C4_​SDA, GP_​H07/I2C3_​SCL, GP_​H06/I2C3_​SDA, GP_​H05/I2C2_​SCL, GP_​H04/I2C2_​SDA, GP_​H03/SX_​EXIT_​HOLDOFF_​N, , GP_​H02/MODEM_​CLKREQ, GP_​H19, GP_​H18, GP_​H17, GP_​H16, GP_​H15/AVS_​I2S1_​SCLK

, GP_​H14/AVS_​I2S2_​RXD, GP_​H13/AVS_​I2S2_​TXD/MODEM_​CLKREQ, GP_​H12/AVS_​I2S2_​SFRM/CNV_​RF_​RESET_​N, GP_​H11/AVS_​I2S2_​SCLK, GP_​H10/CPU_​C10_​GATE_​N, GP_​H01/SD_​SDIO_​PWR_​EN_​N/CNV_​RF_​RESET_​N, GP_​H00, GP_​D09/GSPI2_​CLK/UART0A_​TXD, GP_​D08/GSPI2_​SPI2_​CS0_​N/UART0A_​RXD, GP_​D07, GP_​D06, GP_​D05, GP_​D04, GP_​D03/BK_​3/SBK_​3, GP_​D23/I2C5_​SCL, GP_​D22/I2C5_​SDA, GP_​D21/CNV_​PA_​BLANKING, GP_​D20/CNV_​MFUART2_​TXD, GP_​D02/BK_​2/SBK_​2, GP_​D19/CNV_​MFUART2_​RXD, GP_​D18/AVS_​I2S_​MCLK, GP_​D17, GP_​D16, GP_​D15/CNV_​WCEN, GP_​D14/GSPI2_​CS1_​N, GP_​D13/I2C4B_​SCL, GP_​D12/I2C4B_​SDA, GP_​D11/GSPI2_​MOSI/UART0A_​CTS_​N, GP_​D10/GSPI2_​MISO/UART0A_​RTS_​N, GP_​D01/BK_​1/SBK_​1, GP_​D00/BK_​0/SBK_​0, GP_​C09/UART0_​TXD, GP_​C08/UART0_​RXD, GP_​C07/PMC_​SUSACK_​N, GP_​C06/PMC_​SUSWARN_​N/PMC_​SUSPWRDNACK, GP_​C05, GP_​C04, GP_​C03,GP_​C23/UART2_​CTS_​N/CNV_​MFUART0_​CTS_​N, GP_​C22/UART2_​RTS_​N/CNV_​MFUART0_​RTS_​N, GP_​C21/UART2_​TXD/CNV_​MFUART0_​TXD, GP_​C20/UART2_​RXD/CNV_​MFUART0_​RXD, GP_​C02, GP_​C19/I2C1_​SCL, GP_​C18/I2C1_​SDA, GP_​C17/I2C0_​SCL, GP_​C16/I2C0_​SDA, GP_​C15/UART1_​CTS_​N, GP_​C14/UART1_​RTS_​N, GP_​C13/UART1_​TXD, GP_​C12/UART1_​RXD, GP_​C11/UART0_​CTS_​N, GP_​C10/UART0_​RTS_​N, GP_​C01, GP_​C00

3.3 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-12

12

µA

CIN

Input Pin Capacitance

10

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

Only for 50 ohm mode

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Only for 50 ohm mode

Rpu

WPU 5K/20K Resistance

1K-50%

5K-70%

20K-35%

1K+100%

5K+70%

20K+35%

Ohm

0.7 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-35%

5K+70%

20K+35%

Ohm

0.3 * VCC

1.8 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-12

12

µA

CIN

Input Pin Capacitance

10

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

Only for 50 ohm mode

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Only for 50 ohm mode

Rpu

WPU 5K/20K Resistance

1K-50%

5K-70%

20K-35%

1K+100%

5K+70%

20K+35%

Ohm

0.7 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-35%

5K+70%

20K+35%

Ohm

0.3 * VCC

Notes:
  1. For GPIO supported voltages, refer to General Purpose Input and Output (GPIO)
  2. When eSPI is enabled, SX_​EXIT_​HOLDOFF_​N functionality is not available, and assertion of the signal will not impact Sx exit flows. 
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to the General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.

Associated Signals1: GP_​A09/SMB_​ALERT_​N, GP_​A08/SMB_​DATA, GP_​A07/SMB_​CLK, GP_​A06/ESPI_​RESET_​N, GP_​A05/ESPI_​CLK, GP_​A04/ESPI_​CS_​N, GP_​A03/ESPI_​IO_​3, GP_​A02/ESPI_​IO_​2, GP_​A19/PCHHOT_​N, GP_​A18/USB_​OC0_​N, GP_​A17/DDI0_​HPD, GP_​A16/DDI1_​HPD/TIME_​SYNC_​1, GP_​A15, GP_​A14/USB_​OC3_​N, GP_​A13/USB_​OC2_​N, GP_​A12/USB_​OC1_​N, GP_​A11/CPU_​GP_​1, GP_​A10/CPU_​GP_​0, GP_​A01/ESPI_​IO_​1, GP_​A00/ESPI_​IO_​0, GP_​E09/SML_​CLK0/SATA_​1_​GP, GP_​E08/SATA_​0_​GP, GP_​E07/SATA_​1_​DEVSLP, GP_​E06/IMGCLKOUT_​3, GP_​E05/SATA_​LED_​N, GP_​E04/IMGCLKOUT_​2, GP_​E03/SATA_​0_​DEVSLP, GP_​E23/CNV_​RGI_​RSP, GP_​E22/CNV_​RGI_​DT, GP_​E21/CNV_​BRI_​RSP, GP_​E20/CNV_​BRI_​DT, GP_​E02/IMGCLKOUT_​1, GP_​E19/IMGCLKOUT_​5/PCIE_​LNK_​DOWN, GP_​E18/DDI2_​DDC_​SDA/BSSB_​LS2_​TX, GP_​E17/DDI2_​DDC_​SCL/BSSB_​LS2_​RX, GP_​E16/DDI1_​DDC_​SDA/BSSB_​LS1_​TX, GP_​E15/DDI1_​DDC_​SCL/BSSB_​LS1_​RX, GP_​E14/DDI0_​DDC_​SDA/BSSB_​LS0_​TX, GP_​E13/DDI0_​DDC_​SCL/BSSB_​LS0_​RX, GP_​E12/IMGCLKOUT_​4/BSSB_​LS3_​TX, GP_​E11/BSSB_​LS3_​RX, GP_​E10/SML_​DATA0, GP_​E01, GP_​E00/IMGCLKOUT_​0

3.3 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-14

14

µA

CIN

Input Pin Capacitance

14

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

Only for 50 ohm mode

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Only for 50 ohm mode

Rpu

WPU 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.7 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.3 * VCC

1.8 V Operation

Input

VIH

Input High Voltage Threshold

0.75 x VCC

V

VIL

Input Low Voltage Threshold

0.25 x VCC

V

IIL

Input Leakage Current

-14

14

µA

CIN

Input Pin Capacitance

14

pF

Output

VOH

Output High Voltage Threshold

VCC - 0.45

VCC

V

IOH=3 mA

Only for 50 ohm mode

VOL

Output Low Voltage Threshold

0.45

V

IOL=-3 mA

Only for 50 ohm mode

Rpu

WPU 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.3 * VCC

Rpd

WPD 5K/20K Resistance

5K-70%

20K-25%

5K+70%

20K+35%

Ohm

0.7 * VCC

Notes:
  1. For GPIO supported voltages, refer to General Purpose Input and Output (GPIO)
  2. If GP_​A[00:06] is used for eSPI it can be configured to 1.8V only otherwise if used as GPIO it can be configured to 3.3V or 1.8V
  3. If GP_​E[11:18] is used for BSSB it can be configured to 1.8V only otherwise if used as GPIO it can be configured to 3.3V or 1.8V
  4. If GP_​E[20:23] is used for CNVi it can be configured to 1.8V only otherwise if used as GPIO it can be configured to 3.3V or 1.8V

Single-Ended Signal DC Characteristics as Inputs or Outputs

Type

Symbol

Parameter

Minimum

Maximum

Unit

Condition

Notes

Associated Signals: INTRUDER_​N, PMC_​RSMRST_​N, PMC_​PCH_​PWROK, PMC_​DSW_​PWROK, SRTCRST_​N

Input

VIH

Input High Voltage Threshold

0.65 x VCCRTC

VCCRTC+0.5

V

4, 6

VIL

Input Low Voltage Threshold

-0.5

0.3 x VCCRTC

V

6

Associated Signals: RTCRST_​N

Input

VIH

Input High Voltage Threshold

0.75 x VCCRTC

V VCCRTC+0.5

V

4, 5, 6

VIL

Input Low Voltage Threshold

-0.5

0.4 x VCCRTC

V

6

Associated Signals: RTCX1

Input

VIH

Input High Voltage Threshold

0.8

1.2

V

VIL

Input Low Voltage Threshold

-0.5

0.1

V

Notes:
  1. The VOH specification does not apply to open-collector or open-drain drivers. Signals of this type must have an external Pull-up resistor, and that is what determines the high-output voltage level.
  2. Input characteristics apply when a signal is configured as Input or to signals that are only Inputs. Output characteristics apply when a signal is configured as an Output or to signals that are only Outputs.
  3. Vpk-pk minimum for XTAL24 = 500 mV
  4. VCCRTC is the voltage applied to the VCCRTC well of the PCH. When the system is in G3 state, it is generally supplied by the coin cell battery. In S5 or greater state, it is supplied by VCCSUS3_​3
  5. VIH min should not be used as the reference point for T200 timing. Refer T200 specification for the measurement point detail
  6. These buffers have input hysteresis. VIH levels are for rising edge transitions and VIL levels are for falling edge transitions.

Signal Characteristics

Symbol

Parameter

Minimum

Maximum

Unit

Conditions

Notes

Associated Signals: PCIe*

9, 10

Gen 1

VTX-DIFF P-P

Differential Peak to Peak Output Voltage

0.8

1.2

V

1

VTX-DIFF P-P - Low

Low power differential Peak to Peak Output Voltage

0.4

1.2

V

VTX_​CM-ACp

TX AC Common Mode Output Voltage (2.5 GT/s)

20

mV

ZTX-DIFF-DC

DC Differential TX Impedance

80

120

Ohm

VRX-DIFF p-p

Differential Input Peak to Peak Voltage

0.12

1.2

V

1

VRX_​CM-ACp

AC peak Common Mode Input Voltage

150

mV

Gen 2

VTX-DIFF P-P

Differential Peak to Peak Output Voltage

0.8

1.2

V

VTX-DIFF P-P - Low

Low power differential Peak to Peak Output Voltage

0.4

1.2

V

ZTX-DIFF-DC

DC Differential TX Impedance

80

120

Ohm

VRX-DIFF p-p

Differential Input Peak to Peak Voltage

0.12

1.2

V

VRX_​CM-ACp

AC peak Common Mode Input Voltage

150

mV

Gen 3

VTX-DIFF P-P

Differential Peak to Peak Output Voltage

0.8

1.3

V

VTX-DIFF P-P - Low

Low power differential Peak to Peak Output Voltage

0.4

1.2

V

ZTX-DIFF-DC

DC Differential TX Impedance

80

120

Ohm

VRX-DIFF p-p

Differential Input Peak to Peak Voltage

Refer to Stressed Voltage Eye Parameters Table in PCIe* Gen 3 industry specifications.

VRX_​CM-ACp

AC peak Common Mode Input Voltage

150

mV

Associated Signals: SATA

VIMIN-Gen1i

Minimum Input Voltage - 1.5 Gb/s internal SATA

325

mVdiff p-p

2

VIMAX-Gen1i

Maximum Input Voltage - 1.5 Gb/s internal SATA

600

mVdiff p-p

2

VIMIN-Gen1m

Minimum Input Voltage - 1.5 Gb/s eSATA

240

mVdiff p-p

2

VIMAX-Gen1m

Maximum Input Voltage - 1.5 Gb/s eSATA

600

mVdiff p-p

2

VIMIN-Gen2i

Minimum Input Voltage - 3.0 Gb/s internal SATA

275

mVdiff p-p

2

VIMAX-Gen2i

Maximum Input Voltage - 3.0 Gb/s internal SATA

750

mVdiff p-p

2

VIMIN-Gen2m

Minimum Input Voltage - 3.0 Gb/s eSATA

240

mVdiff p-p

2

VIMAX-Gen2m

Maximum Input Voltage - 3.0 Gb/s eSATA

750

mVdiff p-p

2

VIMIN-Gen3i

Minimum Input Voltage - 6.0 Gb/s internal SATA

240

mVdiff p-p

2

VIMAX-Gen3i

Maximum Input Voltage - 6.0 Gb/s internal SATA

1000

mVdiff p-p

2

VOMIN-Gen1i,m

Minimum Output Voltage 1.5 Gb/s internal and eSATA

400

mVdiff p-p

3

VOMIN-Gen2i,m

Minimum Output Voltage 3.0 Gb/s internal and eSATA

400

mVdiff p-p

3

VOMIN-Gen3i

Minimum Output Voltage 6.0 Gb/s internal SATA

200

mVdiff p-p

3

VOMAX-Gen3i

Maximum Output Voltage 6.0 Gb/s internal SATA

900

mVdiff p-p

3

Associated Signals: USB 2.0

VDI

Differential Input Sensitivity

0.2

V

4, 6

VCM

Differential Common Mode Range

0.8

2.5

V

5, 6

VSE

Single-Ended Receiver Threshold

0.8

2

V

6

VCRS

Output Signal Crossover Voltage

1.3

2

V

6

VOL

Output Low Voltage

0.4

V

IOL=5 mA

6

VOH

Output High Voltage

3.3V – 0.5

V

IOH=-2 mA

6

VHSSQ

HS Squelch Detection Threshold

100

150

mV

7

VHSDSC

HS Disconnect Detection Threshold

525

625

mV

7

VHSCM

HS Data Signaling Common Mode Voltage Range

-50

500

mV

7

VHSOI

HS Idle Level

-10

10

mV

7

VHSOH

HS Data Signaling High

360

440

mV

7

VHSOL

HS Data Signaling Low

-10

10

mV

7

VCHIRPJ

Chirp J Level

700

1100

mV

7

VCHIRPK

Chirp K Level

-900

-500

mV

7

New: VDI VCM, VSE, VCRS, VOL, VOH are USB 2.0 FS/LS electrical characteristic.

Associated Signals: USB 3.2

VTX-DIFF-PP

Differential Peak to Peak Output Voltage

0.8

1.2

V

VTX-DIFF P-P - Low

Low power differential Peak to Peak Output Voltage

0.4

1.2

V

8

VTX_​CM-Acp-p

TX AC Common Mode Output Voltage (5GT/s)

100

mV

ZTX-DIFF-DC

DC Differential TX Impedance

72

120

Ohm

VRX-DIFF p-p

Differential Input Peak to Peak Voltage

0.1

1.2

V

VRX_​CM-ACp

AC peak Common Mode Input Voltage

150

mV

Notes:
  1. PCI Express* mVdiff p-p = 2*|PCIE[x]_​TXP – PCIE[x]_​TXN|; PCI Express* mVdiff p-p = 2*|CIE[x]_​RXP – PCIE[x]_​RXN|
  2. SATA Vdiff, RX (VIMAX/VIMIN) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP – SATA[x]RXN|.
  3. SATA Vdiff, tx (VOMIN/VOMAX) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]TXP – SATA[x]TXN|
  4. VDI = | USBPx[P] – USBPx[N] |
  5. Includes VDI range.
  6. Applies to Low-Speed/Full-Speed USB.
  7. Applies to High-Speed USB 2.0.
  8. USB 3.2 mVdiff p-p = 2*|USB3Rp[x] – USB3Rn[x]|; USB 3.1 mVdiff p-p = 2*|USB3Tp[x] – USB3Tn[x]|
  9. For PCIe*, GEN1, GEN and GEN3 correspond to the PCIe base specification revision 1, 2 and 3.
  10. PCIe* specifications are also applicable to the LAN port.
  11. Measurement taken from single-ended waveform on a component test board.
  12. Measurement taken from differential waveform on a component test board.
  13. VCross is defined as the voltage where Clock = Clock#.
  14. Only applies to the differential rising edge (that is, Clock rising and Clock# falling).
  15. The maximum voltage including overshoot.
  16. The minimum voltage including undershoot.
  17. The total variation of all VCross measurements in any particular system. Note that this is a subset of VCross MIN/MAX (VCross absolute) allowed. The intent is to limit VCross induced modulation by setting VCross_​Delta to be smaller than VCross absolute.