Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately after Reset

S3/S4/S5

FSPI_​MOSI_​IO0

Primary

Hi-Z

Internal PU,

then Driven

Low

Driven Low

FSPI_​MISO_​IO1

Primary

Hi-Z

Internal Pull-up

Internal Pull-up

FSPI_​IO2

Primary

Hi-Z

Internal Pull-up

Internal Pull-up

FSPI_​IO3

Primary

Hi-Z

Internal Pull-up

Internal Pull-up

FSPI_​CLK

Primary

Internal Pulldown

Driven Low

Driven Low

FSPI_​CS0_​N

Primary

Internal Pulldown

Driven High

Driven High

FSPI_​CS1_​N

Primary

Internal Pulldown

Driven High

Driven High

FSPI_​CS2_​N

Primary

Internal Pulldown

Driven High

Driven High

Notes:
  1. Reset reference for primary well pins is PMC_​RSMRST_​N.