Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately after Reset1

S3/S4/S5

Deep Sx

GSPI0_​CS0_​N,

GSPI0_​CS1_​N,

GSPI1_​CS0_​N,

GSPI1_​CS1_​N,

GSPI2_​CS0_​N,

GSPI2_​CS1_​N

Primary

Undriven

Undriven

Undriven

OFF

GSPI2_​CLK,

GSPI1_​CLK,

GSPI0_​CLK

Primary

Undriven

Undriven

Undriven

OFF

GSPI2_​MISO,

GSPI1_​MISO,

GSPI0_​MISO

Primary

Undriven

Undriven

Undriven

OFF

GSPI2_​MOSI,

GSPI1_​MOSI,

GSPI0_​MOSI

Primary

Internal Pull-down

Driven Low

Internal Pull-down

OFF

Notes:
  1. Reset reference for primary well pins is PMC_​RSMRST_​N.