Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

PECI DC Characteristics

The PECI interface operates at a nominal voltage set by VccST. The set of DC electrical specifications shown in the following table is used with devices normally operating from a VccST interface supply.

VccST nominal levels will vary between processor families. All PECI devices will operate at the VccST level determined by the processor installed in the system.

Note: PECI supported frequency range is 3.2 KHz - 1 MHz

PECI DC Electrical Limits

Associated Signal: PECI

Symbol

Definition and Conditions

Minimum

Maximum

Units

Notes1

Rup

Internal pull up resistance

-

39.58

Ω

3

Vin

Input Voltage Range

-0.15

Vcc + 0.15

V

-

Vhysteresis

Hysteresis

0.15 * Vcc

V

-

VIL

Input Voltage Low- Edge Threshold Voltage

0.3 * Vcc

V

-

VIH

Input Voltage High- Edge Threshold Voltage

0.7 * Vcc

V

-

Cbus

Bus Capacitance per Node

10

pF

-

Cpad

Pad Capacitance

0.7

1.8

pF

-

Ileak

leakage current

50

uA

-

Notes:
  1. VccST supplies the PECI interface. PECI behavior does not affect VccST min/max specifications.
  2. The leakage specification applies to powered devices on the PECI bus.
  3. The PECI buffer internal pull up resistance measured at 0.75* VccST.

Input Device Hysteresis

The input buffers in both client and host models should use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design.

Input Device Hysteresis