Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

Pin Strap

The following signals are used for static configuration. They are sampled at the rising edge of PMC_​DSW_​PWROK, PMC_​RSMRST_​N, or PMC_​PCH_​PWROK to select configuration and then revert later to their normal usage. To invoke the associated mode, the signal should meet both set up and hold time of 1us, with respect to the rising edge of the sampling signal.

Pin Straps

Signal

Usage

When Sampled

Comment

GP_​C01

Top Swap Override

Rising edge of PMC_​PCH_​PWROK

The strap has a 20 kohm ± 30% internal pull-down.

0 = Disable “Top Swap” mode. (Default)

1 = Enable “Top Swap” mode. This inverts an address on access to SPI and firmware hub, so the processor believes it fetches the alternate boot block instead of the original boot-block. PCH will invert A16 (default) for cycles going to the upper two 64-KB blocks in the FWH or the appropriate address lines (A16, A17, or A18) as selected in Top Swap Block size soft strap.

Notes:
  1. The internal pull-down is disabled after PCH_​PWROK is high.
  2. Software will not be able to clear the Top Swap bit until the system is rebooted.
  3. The status of this strap is readable using the Top Swap bit (Bus0, Device31, Function0, offset DCh, bit4).

This signal is in the primary well.

GP_​C02

No Reboot

Rising edge of PMC_​PCH_​PWROK

The strap has a 20 kohm ± 30% internal pull-down.

0 = Disable “No Reboot” mode. (Default)

1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

Notes:
  1. The internal pull-down is disabled after PCH_​PWROK is high.
  2. This signal is in the primary well.

GP_​C08/UART0_​RXD

TLS Confidentiality

Rising edge of PMC_​RSMRST_​N

This strap has a 20 kohm ± 30% internal pull-down.

0 = Disable Intel® CSE Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). (Default)

1 = Enable Intel® CSE Crypto Transport Layer Security (TLS) cipher suite (with confidentiality).

Notes:
  1. The internal pull-down is disabled after PMC_​RSMRST_​N de-asserts.
  2. This signal is in the primary well.

GP_​C09/UART0_​TXD

eSPI Disable

Rising edge of PMC_​RSMRST_​N

This strap has a 20 kohm ± 30% internal pull-down.

0 = Enable eSPI. (Default)

1 = Disable eSPI.

Notes:
  1. The internal pull-down is disabled after PMC_​RSMRST_​N de-asserts.
  2. This signal is in the primary well.

GP_​C10/UART0_​RTS_​N

Reserved

Rising edge of PMC_​RSMRST_​N

External pull-up is required. Recommend 100 K if pulled up to 3.3 V or 75 K if pulled up to 1.8 V.

This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

There is no internal termination.

GP_​C13/UART1_​TXD

CPUNSSC Clock Frequency

Rising edge of PMC_​RSMRST_​N

This strap has a 20 kohm ± 30% internal pull-down.

0 = 38.4 MHz clock (direct from crystal) (default)

1 = 19.2 MHz clock (derived from 38.4 MHz crystal)

Notes:
  1. The internal pull-down is disabled after PMC_​RSMRST_​N de-asserts.
  2. When used as PCHHOT# and strap low, a 150 K pull-up is needed to ensure it does not override the internal pull-down strap sampling.
  3. This signal is in the primary well.

GP_​D08/SIO_​SPI2_​CS0_​N/UART0A_​RXD

Reserved

Rising edge of PMC_​RSMRST_​N

External pull-up is required. Recommend 100 K if pulled up to 3.3 V or 75 K if pulled up to 1.8 V.

This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

There is no internal termination.

GP_​D09/SIO_​SPI2_​CLK/SIO_​UART0A_​TXD

Reserved

Rising edge of PMC_​RSMRST_​N

External pull-up is required. Recommend 100 K if pulled up to 3.3 V or 75 K if pulled up to 1.8 V.

This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

There is no internal termination.

GP_​A15

Flash Descriptor Security Override

Rising edge of PMC_​PCH_​PWROK

This strap has a 20 kohm ± 30% internal pull-down.

0 = Enable security measures defined in the Flash Descriptor. (Default)

1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external Pull-up in manufacturing/debug environments ONLY.

Notes:
  1. The internal pull-down is disabled after PCH_​PWROK is high.
  2. This signal is in the primary well.

GP_​E06/IMGCLKOUT_​3

Reserved

Rising edge of PMC_​RSMRST_​N

External pull-up is required.

This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

There is no internal termination.

GP_​E14/DDI0_​DDC_​SDA

Used for BSSB_​LS0(1.8V) or the display GMBus(3.3V)

Rising edge of PMC_​RSMRST_​N

This strap has 20 K internal pull-down.

0 = GP_​E13/GP_​E14 pins at 1.8 V

1 = GP_​E13/GP_​E14 pins at 3.3 V

Note:This signal is in the primary well.

GP_​E16/DDI1_​DDC_​SDA

Used for BSSB_​LS1(1.8V) or the display GMBus(3.3V)

Rising edge of PMC_​RSMRST_​N

This strap has 20 K internal pull-down.

0 = GP_​E15/GP_​E16 pins at 1.8 V

1 = GP_​E15/GP_​E16 pins at 3.3 V

Note:This signal is in the primary well.

GP_​E18/DDI2_​DDC_​SDA

Used for BSSB_​LS2(1.8V) or the display GMBus(3.3V)

Rising edge of PMC_​RSMRST_​N

This strap has 20 K internal pull-down.

0 =GP_​E17/GP_​E18 pins at 1.8 V

1 = GP_​E17/GP_​E18 pins at 3.3 V

Note:This signal is in the primary well.

GP_​E12/IMGCLKOUT_​4

Used for BSSB_​LS3(1.8V) or the display GMBus(3.3V)

Rising edge of PMC_​RSMRST_​N

This strap has 20 K internal pull-down.

0 = GP_​E11/GP_​E12 pins at 1.8 V

1 = GP_​E11/GP_​E12 pins at 3.3 V

Note:This signal is in the primary well.

GP_​D10

RSVD

Rising edge of PMC_​RSMRST_​N

This strap has 20 K internal pull-down.

Do not pull this pin high on board.

DBG_​PMODE

Reserved

Rising edge of PMC_​RSMRST_​N

This strap has a 20 kohm ± 30% internal pull-up.

This strap should sample high. There should NOT be any on-board device driving it to opposite direction during strap sampling.

Notes:
  1. The internal pull-up is disabled after PMC_​RSMRST_​N de-asserts.
  2. This signal is in the primary well.

GP_​DSW07

Reserved

Rising edge of PMC_​DSW_​PWROK

This strap has a 20 kohm ± 30% internal pull-down.

This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling.

Notes:
  1. The internal pull-down is disabled after DSW_​PWROK is high.
  2. This signal is in the DSW well.

GP_​E00/IMGCLKOUT_​0

XTAL Frequency Selection

Rising edge of PMC_​RSMRST_​N

This strap has a 20 kohm ± 30% internal pull-down.

This strap should not be pulled high since 24 MHz crystal is not supported on the PCH.

0 = 38.4 MHz/19.2 MHz(default)

1 = 24 MHz

Notes:
  1. The internal pull-down is disabled after PMC_​RSMRST_​N de-asserts.
  2. This signal is in the primary well.

GP_​E22/CNV_​RGI_​DT

M.2 CNVi Mode Select

Rising edge of PMC_​RSMRST_​N

A weak external pull-up is required.

0 = Integrated CNVi enabled.

1 = Integrated CNVi disabled.

Note:When a RF companion chip is connected to the PCH CNVi interface. There is no internal termination.

GP_​D11/SPI2_​MOSI/UART0A_​CTS_​N

eSPI Flash Sharing Mode

Rising edge of PMC_​RSMRST_​N

This strap has a 20 kohm ± 30% internal pull-down.

0 = Master Attached Flash Sharing (MAFS) is enabled.

(Default)

1 = Slave Attached Flash Sharing (SAFS) is enabled.

Notes:
  1. The internal pull-down is disabled after PMC_​RSMRST_​N de-asserts.

This signal is in the primary well.

INTRUDER_​N2

SPI Voltage Configuration

SRTCRST_​N

There is no internal pull-up or pull-down on the signal. An external pull-up / pull-down is required.

0 = SPI operation voltage is 3.3 V (10 kohm pull-down to GND)

1 = SPI operation voltage is 1.8 V (1 Mohm pull-up to VCCRTC)

CFG_​00

EAR

-

1 = (Default) Normal Operation;.

0 = Reserved.

CFG_​04

eDP Presense

-

Embedded Display Port Presence Strap

1= (default) disabled.

0=enabled.

Notes:
  1. CFG signals have a default value as ‘1’.

  2. INTRUDER_​N is exclusively used for SPI Voltage Configuration. Chassis Intrusion Detection is not supported.