Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

Signal Description

MIPI CSI Port A and Port C can be configured as x4.

Camera Signals

Camera Signals

Description

MCSI_​A_​CKP

Differential clock (Port A)

MCSI_​A_​CKN

Differential clock (Port A)

MCSI_​A_​D0P

Lane 0 Differential data (Port A)

MCSI_​A_​D0N

Lane 0 Differential data (Port A)

MCSI_​A_​D1P

Lane 1 Differential data (Port A)

MCSI_​A_​D1N

Lane 1 Differential data (Port A)

MCSI_​B_​D1P_​A_​D2P

Differential data (Lane 1 Port B/Lane 2 Port A)

MCSI_​B_​D1N_​A_​D2N

Differential data (Lane 1 Port B/Lane 2 Port A)

MCSI_​B_​D0P_​A_​D3P

Differential data (Lane 0 Port B/Lane 3 Port A)

MCSI_​B_​D0N_​A_​D3N

Differential data (Lane 0 Port B/Lane 3 Port A)

MCSI_​B_​CKP

Differential clock (Port B)

MCSI_​B_​CKN

Differential clock (Port B)

MCSI_​C_​CKP

Differential clock (Port C)

MCSI_​C_​CKN

Differential clock (Port C)

MCSI_​C_​D0P

Lane 0 Differential data (Port C)

MCSI_​C_​D0N

Lane 0 Differential data (Port C)

MCSI_​C_​D1P

Lane 1 Differential data (Port C)

MCSI_​C_​D1N

Lane 1 Differential data (Port C)

MCSI_​D_​D1P_​C_​D2P

Differential data (Lane 1 Port D/Lane 2 Port C)

MCSI_​D_​D1N_​C_​D2N

Differential data (Lane 1 Port D/Lane 2 Port C)

MCSI_​D_​D0P_​C_​D3P

Differential data (Lane 0 Port D/Lane 3 Port C)

MCSI_​D_​D0N_​C_​D3N

Differential data (Lane 0 Port D/Lane 3 Port C)

MCSI_​D_​CKP

Differential clock (Port D)

MCSI_​D_​CKN

Differential clock (Port D)

MCSI_​RCOMP

Compensation Resistor