Intel® 700 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
743835 | 12/22/2023 | Public |
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Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
Audio Voice and Speech
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
Feature Overview
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Functional Description
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Intel® 700 Series Chipset Family PCH
Intel® 700 Series Chipset Family PCH
North PGS = North Flex HSIO PCH Section Covering PCIe/GbE/SATA
South PD = South Flex HSIO PCH Section Covering PCIe/DMI
South U = South Flex HSIO PCH Section Covering USB 3.2
LR = Lane Reversal
“Not Available” = The identified PHY Lane and its associated Flex I/O Lane are not available for any High Speed I/O (HSIO) Interface within the selected Configuration Option
The 46 Flexible HSIO Lanes on
- Up to 28 PCIe* Lanes with a maximum of 20 PCIe* Gen4 Lanes
- Up to eight SATA Lanes (Lanes 0-3 & 4-7)
- A maximum of eight SATA Ports (or devices) can be enabled.
- Up to ten USB 3.2 Gen 1x1/2x1 Lanes
- A maximum of ten USB 3.2 Gen 1x1/2x1 Ports can be enabled
- USB 3.2 Gen 1x1 = 5 GT\s
- USB 3.2 Gen 2x1 = 10 GT\s
- Up to ten USB 3.2 Gen 2x2 Lanes
- A maximum of five USB 3.2 Gen 2x2 Ports can be enabled
- USB 3.2 Gen 2x2 = 20 GT\s
- Up to eight DMI Lanes for x4 and x8 support
- Up to three GbE Lanes
- A maximum of one GbE Port can be enabled