Intel® 700 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
743835 | 12/22/2023 | Public |
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Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
Ballout Definition
8254 Timers
Audio Voice and Speech
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Direct Media Interface
Private Configuration Space Target Port ID
Miscellaneous Signals
Feature Overview
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Functional Description
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
The PCH implements I2C controllers for independent I2C interfaces, I2C0-. Each interface is a two-wire serial interface consisting of a serial data line (SDA) and a serial clock (SCL).
The I2C interfaces support the following features:
- Speed: standard mode (up to 100 Kb/s), fast mode (up to 400 Kb/s), fast mode plus (up to 1 MB/s) and High speed mode (up to 3.2 Mb/s).
- 1.8 V or 3.3 V support (depending on the voltage supplied to the I2C signal group)
- Master I2C operation only
- 7-bit or 10-bit addressing
- 7-bit or 10-bit combined format transfers
- Bulk transmit mode
- Ignoring CBUS addresses (an older ancestor of I2C used to share the I2C bus)
- Interrupt or polled-mode operation
- Bit and byte waiting at all bus speed
- Component parameters for configurable software driver support
- Programmable SDA hold time (tHD; DAT)
- DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)
- 64-byte Tx FIFO and 64-byte Rx FIFO
- SW controlled serial data line (SDA) and serial clock (SCL)
Acronyms | Description |
---|---|
I2C | Inter-Integrated Circuit |
PIO | Programmed Input/Output |
SCL | Serial Clock Line |
SDA | Serial Data Line |
Specification | Location |
---|---|
The I2C Bus Specification, Version 5 | www.nxp.com/documents/user_manual/UM10204.pdf |