Intel® 700 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
743835 | 12/22/2023 | Public |
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Signal Description
Signal Name | Type | Description |
---|---|---|
JTAG Signals | ||
PCH_JTAG_TCK | I/O | Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. |
PCH_JTAG_TMS | I/OD | Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. |
PCH_JTAG_TDI | I/OD | Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. |
PCH_JTAG_TDO | I/OD | Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. |
PCH_JTAGX | I/O | This pin is used to support merged debug port topologies. |
DBG_PMODE | O | ITP Power Mode Indicator. This signal is used to transmit processor and PCH power/reset information to the Debugger. |
I | This pin is used for debug support | |
O | This pin is used for debug support
| |
PREQ# | I/OD | |
PRDY# | I/OD | |
Boundry Scan Sideband Signals | ||
I/O | ||
GPP_J10 / BSSB_LS_RX | I/O |