Intel® 700 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
Signal Description
| Name | Type | Description |
|---|---|---|
| Intel High Definition Audio Signals | ||
| GPP_R4 / HDA_RST# | O | Intel HD Audio Reset: Host H/W reset to internal/external codecs. |
| GPP_R1 / HDA_SYNC / I2S0_SFRM | O | Intel HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. Also used to encode the stream number. |
| GPP_R0 / HDA_BCLK / I2S0_SCLK / HDACPU_BCLK | O | Intel HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel HD Audio controller. |
| GPP_R2 / HDA_SDO / I2S0_TXD / HDA_PROC_SDO | O | Intel HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s. |
| GPP_R3 / HDA_SDI0 / I2S0_RXD / HDACPU_SDI | I | Intel HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
| GPP_R5 / HDA_SDI1 / I2S1_RXD | I | Intel HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
| Intel Display Audio Interface | ||
| HDACPU_BCLK or GPP_R0 / HDA_BCLK / I2S0_SCLK / HDACPU_BCLK | O | Display Audio Bit Clock: Serial data clock generated by the Intel HD Audio controller. PCH supports data rate of up to 96 Mb/s. |
| HDACPU_SDO
or GPP_R2 / HDA_SDO / I2S0_TXD / HDA_PROC_SDO | O | Display Audio Serial Data Out: Serial TDM data output to the codec. PCH supports data rate of up to 96 Mb/s. |
| HDACPU_SDI or GPP_R3 / HDA_SDI0 / I2S0_RXD / HDACPU_SDI | I | Display Audio Serial Data In: Serial TDM data input from the codec. PCH supports data rate of up to 96 Mb/s. |
| I2S/PCM Interface | ||
| GPP_R0 / HDA_BCLK / I2S0_SCLK / HDACPU_BCLK | I/O | I2S/PCM serial bit clock 0:Clock used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_R8 / I2S1_SCLK | I/O | I2S/PCM serial bit clock 1:This clock is used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_D8 / I2S2_SCLK | I/O | I2S/PCM serial bit clock 2:This clock is used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_R1 / HDA_SYNC / I2S0_SFRM | I/O | I2S/PCM serial frame indicator 0: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_R7 / I2S1_SFRM | I/O | I2S/PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_D5 / I2S2_SFRM / CNV_RF_RESET# | I/O | I2S/PCM serial frame indicator 2: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_R2 / HDA_SDO / I2S0_TXD / HDACPU_SDO | O | I2S/PCM transmit data (serial data out)0: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
| GPP_R6 / I2S1_TXD | O | I2S/PCM transmit data (serial data out)1: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
| GPP_D6 / I2S2_TXD / MODEM_CLKREQ | O | I2S/PCM transmit data (serial data out)2: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
| GPP_R3 / HDA_SDI0 / I2S0_RXD / HDACPU_SDI | I | I2S/PCM receive data (serial data in)0: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
| GPP_R5 / HDA_SDI1 / I2S1_RXD | I | I2S/PCM receive data (serial data in)1: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
| GPP_D7 / I2S2_RXD | I | I2S/PCM receive data (serial data in)2: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
| GPP_B11 / I2S_MCLK | O | I2S/PCM Master reference clock: This signal is the master reference clock that connects to an audio codec. |
| DMIC Interface | ||
| GPP_S6 / SNDW4_CLK / DMIC_CLKA0 | O | Digital Mic Clock A0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
| GPP_S4 / SNDW3_CLK / DMIC_CLKA1 | O | Digital Mic Clock A1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
| GPP_S2 / SNDW2_CLK / DMIC_CLKB0 | O | Digital Mic Clock B0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
| GPP_S3 / SNDW2_DATA / DMIC_CLKB1 | O | Digital Mic Clock B1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
| GPP_S7 / SNDW4_DATA / DMIC_DATA0 | I | Digital Mic Data:Serial data input from the digital mic. |
| GPP_S5 / SNDW3_DATA / DMIC_DATA1 | I | Digital Mic Data:Serial data input from the digital mic. |
| SoundWire Interface | ||
| GPP_S0 / SNDW1_CLK | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
| GPP_S1 / SNDW1_DATA | I/O | SoundWire Data: Serial data input from external peripheral devices. |
| GPP_S2 / SNDW2_CLK / DMIC_CLKB0 | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
| GPP_S3 / SNDW2_DATA / DMIC_CLKB1 | I/O | SoundWire Data: Serial data input from external peripheral devices. |
| GPP_S4 / SNDW3_CLK / DMIC_CLKA1 | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
| GPP_S5 / SNDW3_DATA / DMIC_DATA1 | I/O | SoundWire Data: Serial data input from external peripheral devices. |
| GPP_S6 / SNDW4_CLK / DMIC_CLKA0 | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
| GPP_S7 / SNDW4_DATA / DMIC_DATA0 | I/O | SoundWire Data: Serial data input from external peripheral devices. |
| SNDW_RCOMP | I/O | SoundWire RCOMP:200ohm +/- 1% compensation resistor required to ground. |
| Misc | ||
| GPP_B14 / SPKR | O | Speaker Output:Used for connection to external speaker for POST sounds if not using HD_Audio embedded option. |