Problem

If a processor USB Type-C* port is configured in Device Mode (or in DbC mode) and connected to an external USB 3.2 host controller, it may cause the USB port to go into a non-functional state in the following scenarios:

Implication

Due to this erratum, the processor USB Type-C port configured in Device Mode (or in DbC mode) may fail to enumerate or become unavailable.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the xHCI controller is stressed with concurrent traffic across multiple USB ports, the xHCI controller may fail to service USB 2.0 Isochronous IN endpoints within the required service interval.

Implication

Due to this erratum, USB 2.0 isochronous devices connected to the xHCI controller may experience dropped packets.Note: This issue has only been observed with a USB 3.2 Bulk Stream device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Intel^® VT-d remapping hardware does perform Reserved(0) check on Page Snoop (PGSNP) field in scalable-mode Process Address ID (PASID) table entry when Snoop Control capability is defined as not available in the Extended Capability Register Offset 10h bit 7 (ECAP.SC=0)

Implication

There are no known functional implications due to this erratum. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When in HDMI2.1 FRL YUV420 mode, and the previous frame ended with an unexpected odd line, green image corruption may occur.

Implication

Due to this erratum, when using HDMI analyzer, corruption may be observed as green color data, contained within a vertical bar on right side of the analyzer monitor. Intel has not observed and functional issue due to the Erratum.

Workaround

A workaround for this erratum is available in iGFX Driver revision 101.5005 or later.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

Due to this erratum, the processor may fail to enter C3 or deeper package C-States.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may not send LCRD (Link Credit) to the device after the link U0 state recovery is completed if a USB 3.2 device incorrectly stops sending LCRD.

Implication

When this erratum occurs, subsequence transfers from the device may not be completed and the xHCI host controller driver may initiate a host controller reset.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may fail to handle a zero-length data packet when doing concurrent traffic with the following devices connected on three separate root ports:

• USB 3.2 Gen 2x1 (or 2x2) hub with at least two USB 3.2 bulk devices.
• USB 3.2 Gen 2x1 (or 2x2) hub with at least two USB 3.2 bulk devices.
• USB isochronous device that sends zero-length data packets.

Implication

Due to this erratum, the xHCI controller may hang. Intel has only observed this behavior with USB audio offload enabled and USB 2.0 audio devices that send zero-length data packets.

Workaround

None identified. A mitigation for USB 2.0 audio devices using USB audio offload is available in Intel^® Smart Sound Technology driver version 20.40.9509.0 or later.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Re-enabling a port following a link disable or hot reset the PCIe Lane Error Status register (Offset 0xA38) may not be cleared.

Implication

Due to this erratum, the Lane Error Status register may indicate lane errors on some of the Root Ports. Intel has not observed any functional issues due this erratum.

Workaround

None identified. Software should ignore the lane error status register to mitigate this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching between Type-C Display Alt Mode and an Multi-Function Device (MFD) while the system is in S3/S4/S5, the Display may not enumerate.

Implication

When this erratum occurs the Display may be blank. A device unplug and re-plug may be necessary to recover the display.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The PTM Propagation Delay Adaptation Interpretation B (PTMPDAIB) Bit is implemented at Configuration Space (CFG) Offset 158h instead of at 50h as documented in the PCI-SIG PTM Byte Ordering Adaptation Engineering Change Notice (ECN).

Implication

Due to this erratum, End Point Device (EPD) software that implements the PTM Byte Ordering Adaptation ECN may not be able to program their PTMPDAIB Bit correctly since it is located at a different register offset.

Workaround

None identified. To mitigate this issue, EPD software that implements the PTM Byte Ordering Adaptation ECN must access PTMPDAIB at CFG Offset 158h.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A CALL instruction whose target is the next sequential instruction (the same address pushed onto the stack) may not increment the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H, F9H).

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may undercount. Since the CALL is to the next instruction, control flow tracing with the Last Branch Retired (LBR) records should not be affected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On certain types of branch and complex instructions the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H / 7EH / BFH / C0H / DFH / EBH / FBH / F9H) may overcount by 1. Affected instructions include FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD and complex SGX/SMX/CSTATE instructions/flows.

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may overcount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

PCIe Lanes 21 through 28 may fail Gen5 link equalization at high temperatures due to complex lane microarchitectural conditions.

Implication

Due to this erratum, the associated PCIe Gen5 link may exhibit link errors, hang, or fail compliance tests. No issues have been observed when the PCIe link attempts Gen4 or lower.

Workaround

It is possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On platforms that enable System Agent Geyserville (SAGV), a technology that allows load-specific memory speeds, the processor may exhibit unpredictable system behavior.

Implication

When this erratum occurs, the processor exhibits unpredictable system behavior.

Workaround

It is possible for BIOS to work around this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the storage subsystem is configured to operate in RAID 0 or 1 mode, a Message Signaled Interrupt (MSI) from an Intel^® Volume Management Device (Intel^® VMD) owned device may interrupt a core before a previous write from the device is completed.

Implication

Due to this erratum, the platform may experience unpredictable system behavior.

Workaround

None identified. The VMD MSI interrupt-handler should initially perform a dummy register read to the MSI initiator device prior to any writes to ensure proper PCIe ordering.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A non-zero value written to IA32_​MC2_​ADDR (40Ah) and IA32_​MC2_​MISC(40Bh) MSRs may be incorrectly cleared following a warm reset.

Implication

Due to this erratum, software that relies on the IA32_​MC2_​ADDR and IA32_​MC2_​MISC MSR values may not function correctly after a warm reset. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS (Event A4h, UMask 02h) and IDQ_​BUBBLES.* (Event 9Ch, UMask 01h) may not count when the processor is in the C0.2 power sub-state, which is entered via the TPAUSE or UWAIT instructions. This erratum also impacts the accuracy of MSR_​PERF_​METRICS fields Frontend Bound, Backend Bound, and Fetch Latency (MSR 329h, Bits [23:16], [31:24] and [55:48]).

Implication

Due to this erratum, these performance monitoring events and the fields in MSR_​PERF_​METRICS may be inaccurate.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events IDQ.MS_​UOPS, IDQ.MS_​SWITCHES, and IDQ.MS_​CYCLES_​ANY (Event 79h, UMask 30h) may undercount MS_​UOPS that come from the Decode Stream Buffer (DSB).

Implication

Due to this erratum, performance monitoring counters may report counts lower than expected.

Workaround

None identified. Performance monitoring event UOPS_​RETIRED.MS may be used instead.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor may not have sufficient display bandwidth to support display audio when using HDMI2.1 FRL (Fixed Rate Link) with a 144Hz display with reduced blanking interval.

Implication

Due to this erratum, intermittent or complete loss of audio may occur.

Workaround

A mitigation has been identified for this erratum and may be available in a software update.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

P-core frequency may not be updated after resuming from PKG C6.

Implication

Due to this erratum, P-core may unexpectedly remain in Low Frequency Mode (LFM).

Workaround

A BIOS code change has been identified and may be implemented as a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the I2S interface is in device mode, the audio controller may not be correctly configured if the audio codec requires high frame polarity.

Implication

Due to this erratum, the left and right audio channels may swap when frame polarity is set to high.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor may fail to correctly thermally throttle when running at maximum turbo frequency.

Implication

Due to this erratum, the system may hang with an Internal Timeout Error Machine Check (IA32_​MCi_​STATUS.MSCOD=080h and IA32_​MCi_​STATUS.MCACOD=0400h) or unpredictable system behavior may occur.

Workaround

None identified. It may be possible for BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

DCU DCACHEL0_​EVICT_​ERR (MSCOD=0100h and MCACOD=0174h) may be observed when the core frequency is operating at Maximum Single Core Turbo Frequency.

Implication

Due to this erratum, the system may signal a fatal DCACHEL0_​EVICT_​ERR machine check exception.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If internal graphics is disabled (Bus 0, Device 2, Function 0) when using a discrete graphics solution, the processor may fail to exit Package C6 state and report a machine check exception with an MCACOD=0402H and MSCOD=0823H.

Implication

Due to this erratum, the processor may hang with a machine check exception.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor exposes certain power sharing capabilities via the Intel Performance Framework. However, the processor may not honor power sharing requests made via SET_​PERF_​PREFERENCE_​MIN and SET_​PERF_​PREFERENCE_​MAX.

Implication

Due to this erratum, software may not achieve its expected processor power allocation.

Workaround

It is possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When performing a warm reset as part of enabling of Intel^® Hyper-Threading, machine check banks may not be initialized correctly.

Implication

Due to this erratum, software that relies on initialized values in machine check banks may not behave as expected.

Workaround

None identified. Software or BIOS can avoid this erratum by performing cold reset when re-enabling Intel^® HT.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, writing a non-zero value to the Time-Stamp Counter (TSC) Deadline counter, IA32-TSC_​DEADLINE MSR (6E0h), may cause timer interrupt following the write.

Implication

Due to this erratum, a unexpected timer interrupt may be signaled.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Packet Stream Boundary (PSB) packet should be generated for every PSBFreq number of trace output bytes. Due to this erratum, PSB packets may be generated only after as many as four times that number of output bytes have been generated.

Implication

Due to this erratum, trace decoder software may see fewer PSB packets than expected. This may lead to the trace decoder software needing to search further to find a starting point to decode or, when used in circular mode, being unable to decode the trace due to lacking any PSB packets.

Workaround

None identified. Software can request more frequent PSB packets by programming PSBFreq (bits[27:24]) of IA32_​RTIT_​CTL MSR (570H) to a value 1/4 of the desired value.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a Processor Trace MODE.EXEC packet is generated due to a change in RFLAGS.IF (interrupt flag) or the CS.L or CS.D bits, the processor may not generate a CYC packet before generating the MODE.EXEC packet.

Implication

Due to this erratum, trace decoder software may not be able to precisely determine when mode changes that involve changing the interrupt flag or the application’s default operand size happened.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC.Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code.

Implication

In this case the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.

Workaround

In order to avoid this erratum programmers should use the XMC synchronization algorithm as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide Section: Handling Self- and Cross-Modifying Code.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, if a warm reset event occurs when an Address Translation invalidation transaction is in progress, the processor may perform a cold reset.

Implication

Due to this erratum, the platform may perform a cold reset, rather than a warm reset. Intel has only observed this behavior in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If software disables the APIC by clearing APIC global enable flag (bit 11) in IA32_​APIC_​BASE (MSR 1Bh) while an interrupt is being delivered, the system may hang with a machine check exception reported in IA32_​​MCi_​​STATUS, with MCACOD (bits [15:0]) value of 0400H, and MSCOD (bits [31:16]) value of 0080H.

Implication

Due to this erratum, the system may hang. Intel has not observed this erratum in any commercial available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Longer exit C-State latency associated with SVID slew rate Fast/8 is not accounted for when handling Latency Tolerance Reporting (LTR) thresholds for processor Die/Pkg C-States.

Implication

Due to this erratum, the guaranteed bandwidth requirement for isochronous I/O devices may be violated.

Workaround

It may be possible for the BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a cache line split load may return incorrect data.

Implication

Due to this erratum, split loads may return incorrect data, which may lead to unpredictable system behavior. Intel has only observed this erratum in a synthetic test environment.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a locked operation, including instructions that use the LOCK prefix, may hang the system.

Implication

The processor may hang with a Internal Timeout Error Machine Check exception (IA32_​MCi_​STATUS.MCACOD = 0400h). Intel has only observed this erratum in a synthetic test environment.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During boot, the initial RC6 exit may cause a system hang.

Implication

Due to this erratum, the processor may hang with a machine check exception with IA32_​​MCi_​​STATUS.MSCOD=0x0096 and IA32_​​MCi_​​STATUS.MCACOD=0402h.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During short string operations, it is possible for the E-core to speculatively access addresses beyond the current 4K page boundary, including pages that may be mapped as UnCachable (UC).

Implication

Due to this erratum, it is possible to speculatively access MMIO space, which may lead to unpredictable system behavior, including IO device malfunction.

Workaround

It is possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When operating at maximum bandwidth and lowest latency memory conditions (e.g., when SAGV is configured in a Gear 2 mode), the processor may not provide the necessary voltage to the System Agent devices supplied by the VccSA voltage rail.

Implication

Due to this erratum, System Agent devices supplied by the VccSA rail may be operate at insufficient voltage, which may lead to unpredictable system behavior.

Workaround

None identified. It is possible for BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor may incorrectly limit the VCCSA and VCCGT rail voltage.

Implication

Due to this erratum, the system may exhibit unpredictable behavior.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor may not meet package Cstate exit latency requirements when processing offline Audio Processing Objects (APOs).

Implication

Due to this erratum, intermediate audio distortions may occur.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

RC6 exit request may not complete when processor is in Package C-state C0.

Implication

Due to this erratum, the processor may hang with a GPSB_​MESSAGE_​CHANNEL_​TIMEOUT machine check exception (MCACOD=0414h, MSCOD=0080h).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a MOV SS or POP SS instruction generated a debug exception, and is not followed by an explicit write to the stack pointer (SP), the processor may fail to deliver the debug exception or, if it does, the DR6 register contents may not correctly reflect the causes of the debug exception.

Implication

Debugging software may fail to operate properly if a debug exception is lost or does not report complete information. Intel has not observed this erratum with any commercially available software.

Workaround

Software should explicitly write to the stack pointer immediately after executing MOV SS or POP SS.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If the processor root port receives an FetchAdd, Swap, or CAS TLP (an atomic operation) that is erroneous, it should generate a UR completion to the downstream requestor. If the TLP has an operand size greater than 4 bytes, the generated UR completion will report an operand size of 4 bytes, which will be interpreted as a malformed transaction.

Implication

When this erratum occurs, the processor may respond with a malformed transaction.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, when using Intel(r) Processor Trace (PT) with single range output larger than 4KB, disabling PT and then enabling PT using the TraceEn bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 0) may cause incorrect output values to be recorded.

Implication

Due to this erratum, a PT trace may contain incorrect values.

Workaround

None identified. Software should avoid using PT with single range output larger than 4KB.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Setting MISC_​FEATURE_​CONTROL.DISABLE_​THREE_​STRIKE_​CNT (bit 11 in MSR 1A4h) does not prevent the three-strike counter from incrementing as documented; instead, it only prevents the signaling of the three-strike event once the counter has expired.

Implication

Due to this erratum, software may be able to see the three-strike logged in the MC3_​STATUS (MSR 40Dh, MCACOD = 400h [bits 15:0]) even when MISC_​FEATURE_​CONTROL.DISABLE_​THREE_​STRIKE_​CNT is set.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A VM Exit that occurs while the processor is serving a user interrupt in non-root mode should set the “asynchronous to instruction execution” bit in the Exit Qualification field in the Virtual Machine Control Structure (bit 16). However, if a VM Exit occurs during processing a user interrupt due to an APIC access, the bit will not be set.

Implication

Due to this erratum, the “asynchronous to instruction execution” bit will not be set if an APIC Access VM Exit occurs while the processor is serving a user interrupt. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor accesses to TME exclude range may be encrypted but not decrypted if mapped to remap range.

Implication

Due to this erratum, the processor exclude range it will be encrypted but will but not decrypted if mapped to remap range.

Workaround

It may be possible for BIOS to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If any thread is in thread C6 while another thread is updating one of the following MSRs, a subsequent transition from single thread operation to multi-thread operation or vice versa might cause that MSR to revert to its previous value. The affected MSRs are: MEMORY_​CONTROL (MSR 33h bit 28), QUIESCE_​CTL1 (MSR 50h) and QUIESCE_​CTL2 (MSR 51h).

Implication

Due to this erratum, the values of the above MSRs may be incorrect. Intel has not observed any functional impact due to this erratum.

Workaround

None identified. Software must ensure that the other thread is not in TC6 when writing this MSR.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, single step on branches (IA32_​DEBUGCTLMSR (Offset 1D9h, bit [1]) and also TF flag in EFLAGS register is set) in guest might be missed when VMM enables notification on VM Exit (IA32_​VMX_​PROCBASED_​CTLS2 MSR, Offset 48Bh, bit [31]) while the dirty access bit is not set for the code page (bit [6] in paging-structure entry).

Implication

When single step is enabled under the above condition, some single step branches will be missed. Intel has only observed this erratum in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When TC10 is enabled, a USB 3.2 device connected to USB Type-C port directly without retimer may not function as expected.

Implication

Due to this erratum, a USB 3.2 device may not function as expected.

Workaround

None identified. It may be possible for the BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If invalid parameters are provided, the PCONFIG instruction should generate a #GP exception. Due to this erratum, the processor may instead set a ZF flag, with EAX reporting failure reasons.

Implication

Due to this erratum, incorrectly configured PCONFIG usage may lead to unexpected error reporting.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching a USB Type-C Display Port (DP) monitor connection between Alt Mode and MFD in S4/S5, the monitor may not be enumerated when resuming from S4/S5.

Implication

Due to this erratum, a DP Monitor may not operate when resuming from S4/S5 and may require a hot plug to recover.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Remapping hardware will report non-recoverable VT-d fault and cause the Zero-Length-Read (ZLR) to be aborted, If a ZLR encounters read-only page in first-stage tables and write-only page in second-stage tables.

Implication

Due to this erratum, device may observe an unexpected abort on a ZLR and a VT-d fault may be indicated. Intel has not observed this erratum with any commercially available software.

Workaround

None identified. System software should not create write only pages in second-stage page tables.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A delay in the availability of LCRD1 (Link Credit 1) from a USB 3.2 hub, with two or more downstream USB 3.2 bulk endpoint devices engaged in SuperSpeedPlus concurrent transfers, may lead to the connected xHCI controller sending the ACK and Status of a transfer packet out of order.

Implication

Due to this erratum, a USB 3.2 bulk endpoint device may not respond to subsequent transfers. It may be possible for a device driver to recover the USB 3.2 device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Disconnecting a USB full-speed device from the USB port while the xHCI controller is in the process of sending the Start of Frame may cause the USB 2.0 functionality to become unresponsive for that specific port.

Implication

Due to this erratum, USB 2.0 devices may not be recognized on the USB port until a host controller reset occurs. Intel has only observed this behavior in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

While in DP2.1 UHBR mode and using the YUV420 format with scaling, displays with a resolution higher than 5K @ 60Hz may show display artifacts.

Implication

Due to this erratum, display artifacts may be seen.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On systems with dual IO mode enabled, SPI0_​IO2 and SPI0_​IO3 may momentarily drive low before these signals are pulled high by internal resistors during boot from the G3 state.

Implication

Due to this erratum, unexpected system behavior may occur on systems when SPI0_​IO2 and SPI0_​IO3 signals are connected to an SPI device.

Workaround

None identified. To mitigate this erratum, do not connect SPI0_​IO2 and SPI0_​IO3 to an SPI device in SPI0 dual IO mode enabled systems.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The UC-lock disable feature (MSR_​MEMORY_​CTRL bit [28] (MSR 33h)) may not cause a fault (#AC(4)) for a page split lock that accesses a page with non-WB memory type if the split lock disable (MSR_​MEMORY_​CTRL bit [29]) is not set.

Implication

Due to this erratum, system software may not be able to fully prevent bus locks due to locks to non-WB memory unless they use the split-lock disable feature to prevent bus locks due to splits. Intel has not observed this erratum with any commercially available software.

Workaround

None identified. Software using the UC-lock disable feature should also enable the split lock disable feature.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When Linear Address Masking (LAM) is enabled, a non-canonical fault may be signaled if there is an access which splits the 64-bit linear address space (and thus touches both linear address FFFF_​FFFF_​FFFF_​FFFFh and 0h).

Implication

Due to this erratum, software may receive an unexpected exception on such accesses. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under certain conditions, a VM exit following execution of the MOV to CR8 instruction may unexpectedly result in setting the Valid bit (bit 31) of the IDT-Vectoring Information Field in the Virtual Machine Control Structure (VMCS).

Implication

Depending on the operation of the virtual-machine monitor (VMM), this may result in unexpected VM behavior.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When reporting a machine check in the module level caches (IA32_​MC1_​STATUS, MSR 405H), a Compound Error Code of type Cache Hierarchy Error will be reported with a Level (LL) Sub-field of 0b10[L2] instead of 0b01[L1].

Implication

Due to this erratum, system software relying on this data, may wrongly categorize the cache level in which the error was reported. The severity of the error will be reported accurately.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During PCIe device L0 exit, PCIe Latency Tolerance Reporting (LTR) may not update correctly, resulting in the processor not entering Package State C3 or deeper.

Implication

Due to this erratum, higher than expected power consumption may occur.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On a system with acoustic noise mitigation Voltage Regulator (VR) Slow Slew Rate (SSR) enabled, the latency values may not be correctly calibrated.

Implication

Due to this erratum , the system may experience lower than expected Deepest Run-time Idle Platform State (DRIPS) leading to a higher than expected power consumption.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a core may encounter incorrect data when other cores in the system are entering Core C6 or deeper sleep states.

Implication

When this erratum occurs, unpredictable system behavior may be observed. Intel has only observed this behavior in a synthetic test environment.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Geyserville transition during power state package C6 exit may result in an incorrect iGFX initialization.

Implication

Due to this erratum, the system may hang with a bug check error VIDEO_​TDR_​FAILURE (0x116).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Performance Monitoring events, MEM_​BOUND_​STALLS_​LOAD (EventID: 34h) and MEM_​BOUND_​STALLS_​IFETCH (EventID: 35h), and their subevents, will undercount the number of cycles of core initiated requests with latencies that exceed 256 cycles. A CMASK value of 255 may be used to count instances of this erratum.

Implication

Due to this erratum, software monitoring the events for Memory Bound Stalls may undercount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When software executes Repeat Scan String Byte (REP SCASB) or Repeat Compare String Byte (REP CMPSB) instructions on a core, another core or thread may modify the memory being accessed.

Implication

Due to this erratum, the SCASB or the CMPSB instruction may return incorrect results.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a USB 3.2 device initiates flow control and is connected to the USB Type C* Sub System, the xHCI controller may temporarily pause USB 3.2 bulk transfers until the next micro-frame after the device ends flow control.

Implication

Due to this erratum, USB 3.2 bulk transfers may be temporary paused.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the Intel® Processor Trace (Intel® PT) CR3-filtering mechanism is enabled using the CR3Filter bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 7), CR3 control register bits [63:52] are not compared with the IA32_​RTIT_​CR3_​MATCH MSR (MSR 572h) value.

Implication

Due to this erratum, software that relies upon the IA32_​RTIT_​CTL MSR (bit 7) may function incorrectly.

Workaround

None identified. Software may mitigate this erratum by copying the CR3 register value into IA32_​RTIT_​CR3_​MATCH MSR.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When branch tracing is enabled using branch trace store (BTS) during a task switch, the processor reports the linear address of the branch target in the branch record field "Last Branch from" instead of the linear address of the instruction from which branch was taken.

Implication

Due to this erratum, debug tools relying on BTS may misinterpret control flow.

Workaround

None identified. Software should avoid using BTS to determine the accuracy of branch prediction.

Status

For the steppings affected, refer to the Summary Table of Changes.