Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795260 | 12/14/2023 | 001 | Public |
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0) – Offset 254
Refer to Register Field for detail
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:25 | 0h | RO | Reserved (RSVD_0)
|
| 24 | 0h | RO | Reserved |
| 23 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_23) Same description as bit 0 |
| 22 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_22) Same description as bit 0 |
| 21 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_21) Same description as bit 0 |
| 20 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_20) Same description as bit 0 |
| 19 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_19) Same description as bit 0 |
| 18 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_18) Same description as bit 0 |
| 17 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_17) Same description as bit 0 |
| 16 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_16) Same description as bit 0 |
| 15 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_15) Same description as bit 0 |
| 14 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_14) Same description as bit 0 |
| 13 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_13) Same description as bit 0 |
| 12 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_12) Same description as bit 0 |
| 11 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_11) Same description as bit 0 |
| 10 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_10) Same description as bit 0 |
| 9 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_9) Same description as bit 0 |
| 8 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_8) Same description as bit 0 |
| 7 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_7) Same description as bit 0 |
| 6 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_6) Same description as bit 0 |
| 5 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_5) Same description as bit 0 |
| 4 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_4) Same description as bit 0 |
| 3 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_3) Same description as bit 0 |
| 2 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_2) Same description as bit 0 |
| 1 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_1) Same description as bit 0 |
| 0 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_e_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS bit is set. |