Host Software Pad Ownership (HOSTSW_OWN_GPP_V_0) – Offset 144 - 001 - ID:795260 | Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

ID	Date	Version	Classification
795260	12/14/2023	001	Public

Host Software Pad Ownership (HOSTSW_OWN_GPP_V_0) – Offset 144

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved
23	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_23) Same description as bit 0
22	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_22) Same description as bit 0
21	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_21) Same description as bit 0
20	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_20) Same description as bit 0
19	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_19) Same description as bit 0
18	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_18) Same description as bit 0
17	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_17) Same description as bit 0
16	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_16) Same description as bit 0
15	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_15) Same description as bit 0
14	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_14) Same description as bit 0
13	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_13) Same description as bit 0
12	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_12) Same description as bit 0
11	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_11) Same description as bit 0
10	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_10) Same description as bit 0
9	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_9) Same description as bit 0
8	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_8) Same description as bit 0
7	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_7) Same description as bit 0
6	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_6) Same description as bit 0
5	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_5) Same description as bit 0
4	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_4) Same description as bit 0
3	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_3) Same description as bit 0
2	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_2) Same description as bit 0
1	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_1) Same description as bit 0
0	0h	RW	HostSW_Own (HOSTSW_OWN_xxgpp_v_0) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.