THC Interrupt Enable Register (THC_M_PRT_INT_EN) – Offset 1020 - 001 - ID:795260 | Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

ID	Date	Version	Classification
795260	12/14/2023	001	Public

THC Interrupt Enable Register (THC_M_PRT_INT_EN) – Offset 1020

THC Port Interrupt Enable Register

Bit Range	Default	Access	Field Name and Description
31:30	0h	RO	Reserved (RSVD_31_30) Reserved.
29	1h	RW	Enable THC Transaction Error Reporting with Interrupt (TXN_ERR_INT_EN) b0: Disable THC Transaction Error Reporting Interrupt b1: Enable HCI Transaction Error Reporting Interrupt Note:The Interrupt enable is also qualified by the MSIE or Line Interrupt Enable. When all these enables are set and when THC_TXN_ERR_INT_STS is set, an interrupt will be sent to SW.
28:17	0h	RO	Reserved
16	0h	RW	Enable THC Fatal Error Reporting with Interrupt (FATAL_ERR_INT_EN) b0: Disable THC Fatal Error Reporting Interrupt b1: Enable THC Fatal Error Reporting Interrupt Note:The Interrupt enable is also qualified by the MSIE or Line Interrupt Enable. When all these enables are set and when THC_FATAL_ERR_INT_STS is set, an interrupt will be sent to SW.
15:14	0h	RO	Reserved
13	1h	RW	PRD Entry Error Interrupt Enable (PRD_ENTRY_ERR_INT_EN) Enable PRD Entry Error Reporting with Interrupt
12	1h	RW	Buffer Overrun Error Interrupt Enable (BUF_OVRRUN_ERR_INT_EN) Enable THC Buffer Overrun Error Reporting with Interrupt
11	0h	RO	Reserved
10	1h	RW	Frame Babble Error Interrupt Enable (FRAME_BABBLE_ERR_INT_EN) Enable Frame Babble Error Reporting with Interrupt
9	1h	RW	Invalid Device Entry Interrupt Enable (INVLD_DEV_ENTRY_INT_EN) Enable Invalid Device Register Error Reporting with Interrupt
8:4	0h	RO	Reserved
3	0h	RW	Stop on Frame Babble (SOFB) When set, HW will clear the Start bit, upon detection of a frame babble, and stop read DMA operations. It will stop both DMA engine.
2	1h	RW	Stop on Invalid Device Register (SIDR) When set, HW will clear the Start bit, upon detection of a invalid device register, and stop read DMA operations. It will stop both DMA engine.
1	0h	RW	Stop on THC buffer overrun (SBO) When set, HW will clear the Start bit, upon detection of a buffer overrun, and stop read DMA operations. It will stop both DMA engine.
0	0h	RW	Stop on Invalid PRD entry (SIPE) When set, HW will clear the Start bit, upon detection of an invalid PRD entry, and stop read DMA operations. It will stop both DMA engine.