12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

Datasheet

ID Date Version Classification
655258 28/10/2021 00:00:00 Public Content

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Document Table of Contents

Data Swapping

By default, the processor supports on-board data swapping in two manners (for all segments and DRAM technologies):

  • Bit swapping is allowed within each Byte for all DDR technologies.
  • DDR4: Byte swapping is allowed within each x64 Channel.
  • DDR5: Byte swapping is allowed within each x32 Channel
  • ECC bits swap is allowed within ECC byte/nibble: DDR4 ECC[7..0] and DDR5 ECC[3..0].