12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

Datasheet

ID Date Version Classification
655258 28/10/2021 00:00:00 Public Content

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Document Table of Contents

Processor Power Rails

Power Rail

Description

S Processor Line Controls

VccCORE

Processor IA Cores Power Rail

SVID

VccGT

Graphic Power Rail

SVID

VccIN_​AUX3

Support internal FIVR’s 1, SA, PCIe, Display IO and other internal Blocks.

PCH VID

VccSA 1

Processor System Agent Power Rail

-----

Vcc1P05_​PROC4

Sustain and Sustain Gated Power Rail

Fixed

Vcc1p8_​PROC

PCIE PHY Power 1.8V Rail

Fixed

VccANA Support internal Analog rails, TCSS, Display, PCIE and other internal Blocks ------
VccMIPILP DDI PHY power rail for MIPI DSI interface ------

VDD2

Integrated Memory

Controller Power Rail

Fixed (Memory technology dependent)

Notes:
  1. FIVR = Fully Integrated Voltage Regulator. For details, refer to Voltage Regulator.
  2. VccIN_​AUX has a few discrete voltages defined by PCH VID.
  3. VCC1P05_​PROC, for S processor the power rail is connected to a platform voltage regulator to supply power to the sustaining power rails.

  4. VccMIPILP: When MIPI DSI interface is been used, this power rail should be connected to 1.24 V rail.