Package Mechanical Attributes

12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
655258	05/25/2022		Public

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The S Processor Lines use a Flip Chip technology available in a Land Grid Array (LGA) package. The following table provides an overview of the package mechanical attributes. For specific dimensions (die size, die location, and so on), refer to the processor package mechanical drawings.

S LGA Processor Package Mechanical Attributes

Package	Parameter	S LGA Processor Line
Package Technology	Package Type	Flip Chip Land Grid Array
	Interconnect	Land Grid Array (LGA)
	Lead Free	N/A
	Halogenated Flame Retardant Free	Yes
Package Configuration	Solder Ball Composition	N/A
	Ball/Pin Count	1700
	Grid Array Pattern	Grid Array
	Land Side Capacitors	Yes
	Die Side Capacitors	Yes
	Die Configuration	Single Die Single-Chip Package with HIS
Package Dimensions	Nominal Package Size	45.0 x 37.5 mm
	Z	Substrate Z=1.116 mm +/-0.95 Die Z is 0.37 mm
	Minimum Ball/Pin pitch	0.8 mm

Parameter	Minimum	Maximum
Static Compressive per Contact	0.098 N [10gf]	0.254 N [25gf]
Static Pre-Load Compressive	400 N [80 lbf; End of life]	845 N [190 lbf; Beginning of life]
Static Total Compressive	534 N [120 lbf, Beginning of Life] 400 N [80 lbf; End of life]	1068 N [240 lbf; Beginning of life]
Dynamic Compressive	N/A	489.5 N [110 lbf]
Board Transient Bend Strain	N/A	600ue
Maximum Heatsink Mask	N/A	550 g
PnP cover vertical removal for SMT	0.5 lb	Not recommended for system assy

The P/H/U Processor Lines use a Flip Chip technology available in a Ball Grid Array (BGA) package. The following table provides an overview of the package mechanical attributes. For specific dimensions (die size, die location, and so on), refer to the processor package mechanical drawings.

H/P/U15 - Processor Package Mechanical Attributes

Package	Parameter	P/H/U15 Processor Line
Package Technology	Package Type	Flip Chip Ball Grid Array
	Interconnect	Ball Grid Array (BGA)
	Lead Free	Yes
	Halogenated Flame Retardant Free	Yes
Package Configuration	Solder Ball Composition	SAC405
	Ball/Pin Count	1744
	Grid Array Pattern	Balls anywhere
	Land Side Capacitors	Yes
	Die Side Capacitors	No
	Die Configuration	2 Dice Multi Chip package (MCP)
Package Dimensions	Nominal Package Size	25 x 50 mm
	Z	Substrate Z = 0.594+/-0.08mm 1.185±0.096 (BOTTOM OF BGA TO TOP OF DIE)
	Minimum Ball/Pin pitch	0.65 mm BP

The U9 Processor Lines use a Flip Chip technology available in a Ball Grid Array (BGA) package. The following table provides an overview of the package mechanical attributes. For specific dimensions (die size, die location, and so on), refer to the processor package mechanical drawings.

U9 - Processor Package Mechanical Attributes

Package	Parameter	U9 Processor Line
Package Technology	Package Type	Flip Chip Ball Grid Array
	Interconnect	Ball Grid Array (BGA)
	Lead Free	Yes
	Halogenated Flame Retardant Free	Yes
Package Configuration	Solder Ball Composition	SAC405
	Ball/Pin Count	1781
	Grid Array Pattern	Balls anywhere
	Land Side Capacitors	Yes
	Die Side Capacitors	No
	Die Configuration	2 Dice Multi Chip package (MCP)
Package Dimensions	Nominal Package Size	19 x 28.5 mm
	Z	Substrate Z = 584±0.065 1.033±0.079 (BOTTOM OF BGA TO TOP OF DIE)
	Minimum Ball/Pin pitch	0.4 mm BP