12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

PECI DC Characteristics

The PECI interface operates at a nominal voltage set by Vcc1p05_​PROC. The set of DC electrical specifications shown in the following table is used with devices normally operating from a Vcc1P05_​PROC interface supply.

Vcc1p05_​PROC nominal levels will vary between processor families. All PECI devices will operate at the Vcc1p05_​PROC level determined by the processor installed in the system.

PECI DC Electrical Limits

Symbol

Definition and Conditions

Minimum

Maximum

Units

Notes1

Rup

Internal pull up resistance

15

45

Ω

3

Vin

Input Voltage Range

-0.15

Vcc1p05_​PROC

+ 0.15

V

-

Vhysteresis

Hysteresis

0.1 * Vcc1p05_​PROC

V

-

VIL

Input Voltage Low- Edge Threshold Voltage

0.275 * Vcc1p05_​PROC

0.525 *

Vcc1p05_​PROC

V

-

VIH

Input Voltage High- Edge Threshold Voltage

0.550 * Vcc1p05_​PROC

0.725

*Vcc1p05_​PROC

V

-

Cbus

Bus Capacitance per Node

10

pF

-

Cpad

Pad Capacitance

0.7

1.8

pF

-

Ileak000

leakage current @ 0 V

0.25

mA

-

Ileak100

leakage current @ Vcc1p05

0.15

mA

-

Notes:
  1. Vcc1p05_​PROC supplies the PECI interface. PECI behavior does not affect Vcc1p05_​PROC minimum / maximum specifications.
  2. The leakage specification applies to powered devices on the PECI bus.
  3. The PECI buffer internal pull up resistance measured at 0.75* Vcc1p05_​PROC.

Input Device Hysteresis

The input buffers in both client and host models should use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design.

Input Device Hysteresis