| DDR0_DQ0[7:0] DDR0_DQ1[7:0] DDR0_DQ2[7:0] DDR0_DQ3[7:0] DDR0_DQ4[7:0] DDR0_DQ5[7:0] DDR0_DQ6[7:0] DDR0_DQ7[7:0] DDR0_DQ8[7:0] DDR1_DQ0[7:0] DDR1_DQ1[7:0] DDR1_DQ2[7:0] DDR1_DQ3[7:0] DDR1_DQ4[7:0] DDR1_DQ5[7:0] DDR1_DQ6[7:0] DDR1_DQ7[7:0] DDR1_DQ8[7:0] | Data Buses: Data signals interface to the SDRAM data buses. Example: DDR0_DQ2[5] refers to DDR channel 0, Byte 2, Bit 5. | I/O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_DQSP[8:0] DDR1_DQSP[8:0] DDR0_DQSN[8:0] DDR1_DQSN[8:0] | Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions. Example: DDR0_DQSP0 refers to DQSP of DDR channel 0, Byte 0. | I/O | DDR4 | Diff | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_CLKN[3:0] DDR0_CLKP[3:0] DDR1_CLKN[3:0] DDR1_CLKP[3:0] | SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM. | O | DDR4 | Diff | S Processor Line |
| DDR0_CLK_N[1:0] DDR0_CLK_P[1:0] DDR1_CLK_N[1:0] DDR1_CLK_P[1:0] | SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM. | O | DDR4 | Diff | P Processor Line H Processor Line U15 Processor |
| DDR0_CKE[3:0] DDR1_CKE[3:0] | Clock Enable: (1 per rank). These signals are used to: - Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-refresh during STR (Suspend to RAM).
| O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_CS[3:0] DDR1_CS[3:0] | Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. | O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_ODT[3:0] DDR1_ODT[3:0] | On Die Termination: (1 per rank). Active SDRAM Termination Control. | O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_MA[16:0] DDR1_MA[16:0] | Address: These signals are used to provide the multiplexed row and column address to the SDRAM. DDR0_MA[16] uses as RAS# signal DDR0_MA[15] uses as CAS# signal DDR0_MA[14] uses as WE# signal DDR1_MA[16] uses as RAS# signal DDR1_MA[15] uses as CAS# signal DDR1_MA[14] uses as WE# signal | O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_ACT# DDR1_ACT# | Activation Command: ACT# HIGH along with CS_N determines that the signals addresses below have command functionality. | O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_BG[1:0] DDR1_BG[1:0] | Bank Group: BG[1:0] define to which bank group an Active, reading, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. | O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_BA[1:0] DDR1_BA[1:0] | Bank Address: BA[1:0] define to which bank an Active, reading, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. | O | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_PAR DDR1_PAR | Command and Address Parity: These signals are used for parity check. | O | A | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR_VREF_CA[3:0] | Memory Reference Voltage for Command and Address | O | A | SE | S Processor Line |
| DDR0_VREF_CA0 DDR1_VREF_CA0 | Memory Reference Voltage for Command and Address | O | A | SE | P Processor Line H Processor Line U15 Processor |
| DDR_VTT_CTL | System Memory Power Gate Control: When signal is high – platform memory VTT regulator is enable, output high. When signal is low - Disables the platform memory VTT regulator in C8 and deeper and S3. | O | A | SE | S Processor Line P Processor Line H Processor Line U15 Processor |
| DDR0_ALERT# DDR1_ALERT# | Alert: This signal is used at command training only. It is getting the Command and Address Parity error flag during training. CRC feature is not supported. | I | DDR4 | SE | S Processor Line P Processor Line H Processor Line U15 Processor |