VIL | Input Low Voltage | — | 0.2*Vdd2 | 0.08*Vdd2 | V | 2, 3, 4 |
VIH | 0 = Input High Voltage | 0.35*Vdd2 | 0.2*Vdd2 | — | V | 2, 3, 4 |
RON_UP(DQ) | Data Buffer pull-up Resistance | 30 | — | 50 | Ω | 5,12 |
RON_DN(DQ) | Data Buffer pull-down Resistance | 30 | — | 50 | Ω | 5,12 |
RODT(DQ) | On-die termination equivalent resistance for data signals | 40 | — | 200 | Ω | 6, 12 |
VODT(DC) | On-die termination DC working point (driver set to receive mode) | 0.1*Vdd2 | — | 0.3*Vdd2 | V | 10 |
RON_UP(CK) | Clock Buffer pull-up Resistance | 30 | — | 45 | Ω | 5, 12 |
RON_DN(CK) | Clock Buffer pull-down Resistance | 30 | — | 45 | Ω | 5, 12 |
RON_UP(CMD) | Command Buffer pull-up Resistance | 30 | — | 45 | Ω | 5, 12 |
RON_DN(CMD) | Command Buffer pull-down Resistance | 30 | — | 45 | Ω | 5, 12 |
RON_UP(CTL) | Control Buffer pull-up Resistance | 30 | — | 45 | Ω | 5, 12 |
RON_DN(CTL) | Control Buffer pull-down Resistance | 30 | — | 45 | Ω | 5, 12 |
RON_UP (SM_PG_CNTL1) | System Memory Power Gate Control Buffer Pull-up Resistance | N/A | — | N/A | Ω | N/A |
RON_DN (SM_PG_CNTL1) | System Memory Power Gate Control Buffer Pull- down Resistance | N/A | — | N/A | Ω | N/A |
ILI | Input Leakage Current (DQ, CK) 0 V 0.2* VDD2 0.8* VDD2 | — | — | 1.1 | mA | — |
DDR0_VREF_DQ DDR1_VREF_DQ DDR_VREF_CA | VREF output voltage | Trainable | V | — |
SM_RCOMP[0] | Command COMP Resistance | 99 | 100 | 101 | Ω | 8 |
SM_RCOMP[1] | Data COMP Resistance | 99 | 100 | 101 | Ω | 8 |
SM_RCOMP[2] | ODT COMP Resistance | 99 | 100 | 101 | Ω | 8 |
- Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency
- VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
- VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
- VIH and VOH may experience excursions above VDD2. However, input signal drivers should comply with the signal quality specifications.
- Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models for I/V characteristics.
- ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards
- The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
- SM_RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_RCOMP[x] resistors are to VSS. Values are pre-silicon estimations and are subject to change.
- SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge must be monotonic.
- SM_VREF is defined as VDD2/2 for DDR4
- RON tolerance is preliminary and might be subject to change.
- Maximum-minimum range is correct but center point is subject to change during MRC boot training.
- Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
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