ATX Version 3.0 Multi Rail Desktop Platform Power Supply
Design Guide
PWR_OK – REQUIRED
PWR_OK is a “power good” signal. This signal shall be asserted high by the power supply to indicate that the +12 VDC, +5 VDC, and +3.3 VDC outputs are within the regulation thresholds listed in Table 4-2 and that sufficient mains energy is stored by the converter to guarantee continuous power operation within the specification for at least the duration specified in Section Section 4.2.9. Conversely, PWR_OK should be de-asserted to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages fall below its voltage threshold, or when mains power has been removed for a time sufficiently long enough, such that power supply operation cannot be guaranteed. The electrical and timing characteristics of the PWR_OK signal are given in Table 4-10.
PSU manufacturers are required to label or tag PSU DG revision or ATX spec revision to show compliance and reflect the timing supported.
Table 4-10. PWR_OK Signal Characteristics
Signal Type | +5 V TTL compatible |
Logic Level Low | < 0.4 V while sinking 4 mA |
Logic Level High | Between 2.4 V and 5 V output while sourcing 200 μA |
High State Output Impedance | 1 kΩ from output to common |
Max Ripple/Noise | 400 mV p-p |