Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
| ID | Date | Version | Classification |
|---|---|---|---|
| 631119 | 21/09/2021 00:00:00 | Public Content |
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Introduction and SKU Definition
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
8254 Timers
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface eSPI
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
Serial ATA (SATA)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Touch Host Controller (THC)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Private Configuration Space Target Port ID
Miscellaneous Signals
Features Supported
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI* SoundWire* Interface
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Functional Description
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Functional Description
Features
PCH S0 Low Power
Power Management Sub-state
PCH and System Power States
SMI#/SCI Generation
C-States
Dynamic 38.4 MHz Clock Control
Sleep States
Event Input Signals and Their Usage
ALT Access Mode
System Power Supplies, Planes, and Signals
Legacy Power Management Theory of Operation
Reset Behavior
Audio DSP Capabilities
The Audio DSP offload engine is an optional feature providing low power DSP functionality and offload the audio / sensor processing operation from host processor. It is exposed as an optional capability feature under the Intel® HD Audio controller allowing the enumeration through the Intel® HD Audio driver software (if implemented). Audio DSP capabilities are listed as follows:
- Audio DSP based on
4 Cadence* Tensilica* LX6 HIFI3 DSP Cores operating up to 400 MHz with3 MB SRAM - Low power support for Intel® Wake on Voice (Intel® WOV)
- Low power audio playback with post processing
- Low power VoIP and circuit switch voice call with pre-processing
- Low power FM radio playback
- Various DSP functions provided by DSP Core: MP3, AAC, etc.
- Host downloadable DSP FW functions
- Voice call processing enhancement
- Sensors algorithm offload / assistance: motion, ambient light, fingerprint, proximity, etc.
- Communication hub offload / assistance: location, peer device detection, Wi-Fi* availability, etc.