Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
| ID | Date | Version | Classification |
|---|---|---|---|
| 631119 | 21/09/2021 00:00:00 | Public Content |
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ISH IPC
The ISH has IPC channels for communication with the Host Processor and Intel® CSME. The functions supported by the ISH IPC block are listed below.
Function 1: Allows for messages and interrupts to be sent from an initiator (such as the ISH) and a target (such as the Intel® CSME). The supported initiator -> target flows using this mechanism are shown in the table below.
| Initiator | Target |
|---|---|
| ISH | Host processor |
| Host processor | ISH |
| ISH | Intel® CSME |
| Intel® CSME | ISH |
Function 2: Provides status registers and remap registers that assist in the boot flow and debug. These are simple registers with dual access read/write support and cause no interrupts.