Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
Memory Map
The following table shows (from the Processor perspective) the memory ranges that the PCH will decode. Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode directly from DMI will be master aborted.
PCIe cycles generated by external PCIe* masters will be positively decoded unless they fall in the PCI-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller's range, it will be forwarded up to DMI. Software must not attempt locks to the PCH’s memory-mapped I/O ranges.
| Memory Range | Target | Dependency/Comments |
|---|---|---|
| 000E 0000 - 000E FFFF | eSPI or SPI | Bit 6 in BIOS Decode Enable Register is set. |
| 000F 0000 - 000F FFFF | eSPI or SPI | Bit 7 in BIOS Decode Enable Register is set. |
| FECX X000 - FECX X040 | I/O(x)APIC inside PCH | XX controlled via APIC Range Select (ASEL) field and APIC Enable (AEN) bit. |
| FECX X000 - FECX XFFF | PCIe* port N (N=1 to 24) | X controlled via PCIe root port N IOxAPIC Range Base/Limit registers and Port N I/OxApic Enable (PAE) is set |
| FEC1 0000 - FEC1 7FFF | PCIe port 1 | PCIe root port 1 I/OxApic Enable (PAE) is set |
| FEC1 8000 - FEC1 FFFF | PCIe port 2 | PCIe root port 2 I/OxApic Enable (PAE) is set |
| FEC2 0000 - FEC2 7FFF | PCIe port 3 | PCIe root port 3 I/OxApic Enable (PAE) is set |
| FEC2 8000 - FEC2 FFFF | PCIe port 4 | PCIe root port 4 I/OxApic Enable (PAE) is set |
| FEC3 0000 - FEC3 7FFF | PCIe port 5 | PCIe root port 5 I/OxApic Enable (PAE) is set |
| FEC3 8000 - FEC3 FFFF | PCIe port 6 | PCIe root port 6 I/OxApic Enable (PAE) is set |
| FEC4 0000 - FEC4 7FFF | PCIe port 7 | PCIe root port 7 I/OxApic Enable (PAE) is set |
| FEC4 8000 - FEC4 FFFF | PCIe port 8 | PCIe root port 8 I/OxApic Enable (PAE) is set |
| FEC5 0000 - FEC5 7FFF | PCIe port 9 | PCIe root port 9 I/OxApic Enable (PAE) is set |
| FEC5 8000 - FEC5 FFFF | PCIe port 10 | PCIe root port 10 I/OxApic Enable (PAE) is set |
| FEC6 0000 - FEC6 7FFF | PCIe port 11 | PCIe root port 11 I/OxApic Enable (PAE) is set |
| FEC6 8000 - FEC6 FFFF | PCIe port 12 | PCIe root port 12 I/OxApic Enable (PAE) is set |
| FEF0 0000 - FEFF FFFF | eSPI or SPI | uCode Patch Region Enable UCPR.UPRE is set |
| FFC0 0000 - FFC7 FFFF FF80 0000 - FF87 FFFF | eSPI or SPI | Bit 8 in BIOS Decode Enable Register is set |
| FFC8 0000 – FFCF FFFF FF88 0000 - FF8F FFFF | eSPI or SPI | Bit 9 in BIOS Decode Enable Register is set |
| FFD0 0000 - FFD7 FFFF FF90 0000 - FF97 FFFF | eSPI or SPI | Bit 10 in BIOS Decode Enable Register is set |
| FFD8 0000 – FFDF FFFF FF98 0000 - FF9F FFFF | eSPI or SPI | Bit 11 in BIOS Decode Enable Register is set |
| FFE0 0000 - FFE7 FFFF FFA0 0000 - FFA7 FFFF | eSPI or SPI | Bit 12 in BIOS Decode Enable Register is set |
| FFE8 0000 – FFEF FFFF FFA8 0000 – FFAF FFFF | eSPI or SPI | Bit 13 in BIOS Decode Enable Register is set |
| FFF0 0000 - FFF7 FFFF FFB0 0000 - FFB7 FFFF | eSPI or SPI | Bit 14 in BIOS Decode Enable Register is set |
| FFFC 0000 - FFFF FFFF | eSPI, SPI, or Intel® CSME | Always enabled. Refer to Table: Boot Block Update Scheme for swappable ranges |
| FFF8 0000 - FFFB FFFF FFB8 0000 - FFBF FFFF | eSPI or SPI | Always enabled. Refer to Table: Boot Block Update Scheme for swappable ranges |
| FF70 0000 - FF7F FFFF FF30 0000 - FF3F FFFF | eSPI or SPI | Bit 3 in BIOS Decode Enable Register is set |
| FF60 0000 - FF6F FFFF FF20 0000 - FF2F FFFF | eSPI or SPI | Bit 2 in BIOS Decode Enable Register is set |
| FF50 0000 - FF5F FFFF FF10 0000 - FF1F FFFF | eSPI or SPI | Bit 1 in BIOS Decode Enable Register is set |
| FF40 0000 - FF4F FFFF FF00 0000 - FF0F FFFF | eSPI or SPI | Bit 0 in BIOS Decode Enable Register is set |
| FED0 X000 - FED0 X3FF | HPET | BIOS determines “fixed” location which is one of four 1 KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h. |
| FED4 0000 - FED4 7FFF | SPI (set by strap) | TPM and Trusted Mobile KBC |
| FED6 0000 – FED6 1FFF | PCH Internal (Intel® Trace Hub (Intel® TH)/xHCI) | Always enabled |
| FED5 0000 - FED5 FFFF | Intel® CSME | Always enabled |
| FED7 0000 - FED7 4FFF | Internal Device | Reserved |
| 128 KB anywhere in 4 GB range | LAN Controller (CSR registers) | Enable via standard PCI mechanism (Device 31:Function 6) |
| 4 KB anywhere in 4 GB range | LAN Controller (LAN space on Flash) | Enable via standard PCI mechanism (Device 31:Function 6) |
| 64 KB anywhere in 64-bit address range | USB Host Controller | Enable via standard PCI mechanism (Device 20, Function 0) |
| 2 MB anywhere in 4 GB range | USB Device Controller | Enable via standard PCI mechanism (Device 20, Function 1) |
| 24 KB anywhere in 4 GB range | USB Device Controller | Enable via standard PCI mechanism (Device 20, Function 1) |
| 16 KB anywhere in 64-bit addressing space | Intel® HD Audio Subsystem | Enable via standard PCI mechanism (Device 31, Function 3) |
| 4 KB anywhere in 64-bit addressing space | Intel HD Audio Subsystem | Enable via standard PCI mechanism (Device 31, Function 3) |
| 64 KB anywhere in 64-bit addressing space | Intel HD Audio Subsystem | Enable via standard PCI mechanism (Device 31, Function 3) |
| 32 Bytes anywhere in 64-bit address range | SMBus | Enable via standard PCI mechanism (Device 31: Function 4) |
| 2 KB anywhere above 64 KB to 4 GB range | SATA Host Controller | AHCI memory-mapped registers. Enable via standard PCI mechanism (Device 23: Function 0) |
| Memory Base/Limit anywhere in 4 GB range | PCI Express Root Ports 1-24 | Enable via standard PCI mechanism |
| Prefetchable Memory Base/Limit anywhere in 64-bit address range | PCI Express Root Ports 1-24 | Enable via standard PCI mechanism |
| 16 Bytes anywhere in 64-bit address range | Intel® CSME #1, #2, #3, #4 | Enable via standard PCI mechanism |
| 4 KB anywhere in 4 GB range | Intel® AMT Keyboard and Text | Enable via standard PCI mechanism (Device 22: Function 3) |
| 16 MB anywhere in 64-bit address range | P2SB | Enable via standard PCI mechanism |
| Eight 4 KB slots anywhere in 64-bit address range | UART, GPI and I2C controllers | Enable via standard PCI mechanism |
| 1 MB (BAR0) or 4 KB (BAR1) in 4GB range | Integrated Sensor Hub | Enable via standard PCI mechanism (Device 19: Function 0) |
| 8 KB slot anywhere in 4 GB range | Integrated Wi-Fi* | Enable via standard PCI mechanism |
| 8 KB slot and 4 KB slot anywhere in 4 GB range | PMC | Enable via standard PCI mechanism |
| 8 KB slot and 4 KB slot anywhere in 4 GB range | Shared SRAM | Enable via standard PCI mechanism |