Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
PCI Express* Port Support Feature Details
Supported PCI Express* Link Configurations
- The PCH PCIe* Link Configuration support will vary depending on the PCH SKU.
- RP# refers to a specific PCH PCI Express* Root Port #; for example RP3 = PCH PCI Express* Root Port 3
- A PCIe* Lane is composed of a single pair of Transmit (TX) and Receive (RX) differential pairs, for a total of four data wires per PCIe* Lane (such as, PCIE[3]_TXP/ PCIE[3]_TXN and PCIE[3]_RXP/ PCIE[3]_RXN make up PCIe Lane 3). A connection between two PCIe* devices is known as a PCIe* Link, and is built up from a collection of one or more PCIe* Lanes which make up the width of the link (such as bundling 2 PCIe* Lanes together would make a x2 PCIe* Link). A PCIe* Link is addressed by the lowest number PCIe* Lane it connects to and is known as the PCIe* Root Port (such as a x2 PCIe* Link connected to PCIe* Lanes 3 and 4 would be called x2 PCIe* Root Port 3).
- The PCIe* Lanes can be configured independently from one another but the max number of configured Root Ports (Devices) must not be exceeded
- Unidentified lanes within a PCIe* Link Configuration are disabled but their physical lanes are used for the identified Root Port
- The PCH PCIe* Root Ports can be configured to map to any of the SRCCLKREQ# PCIe* clock request signals and the CLKOUT_PCIE_P/N PCIe* differential clock signal pairs covered in the “Platform Clocks Design Guidelines” Chapter
- Reference and understand the PCIe* High Speed I/O Multiplexing details covered in the “Flexible HSIO” Chapter
- Lane Reversal Supported Motherboard PCIe* Configurations = 1x4, 2x1+1x2, and 2x2
- Un-used USB 3.2/PCIe and SATA/PCIe Combo Port Lanes must be statically assigned to "Disabled" through their Combo Port Soft Straps using the Intel Flash Image Tool (FIT).