Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID Date Version Classification
631119 21/09/2021 00:00:00 Public Content

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Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction and SKU Definition PCH Controller Device IDs Memory Mapping System Management High Precision Event Timer (HPET) PCH Thermal Sensor Power Delivery Pin Straps Electrical and Thermal Characteristics 8254 Timers Audio Voice and Speech Controller Link Processor Sideband Signals Digital Display Signals Enhanced Serial Peripheral Interface eSPI General Purpose Input and Output Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Gigabit Ethernet Controller Integrated Sensor Hub (ISH) PCH and System Clocks PCI Express* (PCIe*) Power Management Real Time Clock (RTC) Serial ATA (SATA) System Management Interface and SMLink Host System Management Bus (SMBus) Controller Serial Peripheral Interface (SPI) Touch Host Controller (THC) Intel® Serial IO Generic SPI (GSPI) Controllers Testability Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Universal Serial Bus (USB) Connectivity Integrated (CNVi) GPIO Serial Expander Private Configuration Space Target Port ID Miscellaneous Signals
Legal Disclaimer
Revision History
Introduction and SKU Definition
Introduction and SKU Definition Overview SKU Definition Flexible High Speed I/O
Overview
SKU Definition
Flexible High Speed I/O
Flexible High Speed I/O PCH-LP (UP4) PCH-LP (UP3) Flexible I/O Lane Selection
PCH-LP (UP4)
PCH-LP (UP3)
Flexible I/O Lane Selection
PCH Controller Device IDs
Device and Revision ID Table
Device and Revision ID Table
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
Functional Description PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation Handling an Intruder TCO Modes
Handling an Intruder
TCO Modes
High Precision Event Timer (HPET)
Features Supported
Features Supported
Features Supported Timer Accuracy Timer off-load Interrupt Mapping Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer off-load
Interrupt Mapping
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
PCH Thermal Sensor
PCH Thermal Sensor Modes of Operation Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Reporting to an EC Thermal Trip Signal (PCHHOT#)
Modes of Operation
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Reporting to an EC
Thermal Trip Signal (PCHHOT#)
Power Delivery
Power Delivery Power and Ground Signals FIVR
Power and Ground Signals
FIVR
Pin Straps
Electrical and Thermal Characteristics
8254 Timers
8254 Timers Timer Programming Reading from the Interval Timer
Timer Programming
Reading from the Interval Timer
Audio Voice and Speech
Audio Voice and Speech Features Supported Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Features Supported
Features Supported Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support I2S/PCM Interface Intel® Display Audio Interface MIPI* SoundWire* Interface
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI* SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Controller Link
Controller Link Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States External CL_RST# Pin Driven/Open-drained Mode Support
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
External CL_RST# Pin Driven/Open-drained Mode Support
Processor Sideband Signals
Processor Sideband Signals Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Digital Display Signals
Digital Display Signals Signal Description Embedded DisplayPort* (eDP*/MIPI*) Backlight Control Signals Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Embedded DisplayPort* (eDP*/MIPI*) Backlight Control Signals
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Enhanced Serial Peripheral Interface eSPI
Enhanced Serial Peripheral Interface eSPI References Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
References
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Operating Frequency Protocols WAIT States from eSPI Slave In-Band Link Reset Slave Discovery Flash Sharing Mode PECI Over eSPI Multiple OOB Master Channels and Supported Transactions
Operating Frequency
Protocols
WAIT States from eSPI Slave
In-Band Link Reset
Slave Discovery
Flash Sharing Mode
PECI Over eSPI
Multiple OOB Master
Channels and Supported Transactions
General Purpose Input and Output
General Purpose Input and Output Signal Description Functional Description
Signal Description
Functional Description
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation Interrupt / IRQ via GPIO Requirement Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO GPIO Blink (BK) and Serial Blink (SBK) GPIO Ownership Native Function and TERM Bit Setting
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Interrupts Power Management Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Interrupts
Power Management
Error Handling
Programmable SDA Hold Time
Gigabit Ethernet Controller
Gigabit Ethernet Controller Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description GbE PCI Express* Bus Interface Error Events and Error Reporting Ethernet Interface PCI Power Management
GbE PCI Express* Bus Interface
Error Events and Error Reporting
Ethernet Interface
PCI Power Management
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Feature Overview Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Feature Overview
Feature Overview ISH I2C Controllers ISH UART Controller ISH GSPI Controller ISH GPIOs
ISH I2C Controllers
ISH UART Controller
ISH GSPI Controller
ISH GPIOs
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface Power Domains and Management ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
Power Domains and Management
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
PCH and System Clocks
PCH and System Clocks Integrated Clock Controller (ICC) Signal Descriptions I/O Signal Pin States
Integrated Clock Controller (ICC)
Signal Descriptions
I/O Signal Pin States
PCI Express* (PCIe*)
PCI Express* (PCIe*) Signal Description I/O Signal Planes and States PCI Express* Port Support Feature Details Functional Description
Signal Description
I/O Signal Planes and States
PCI Express* Port Support Feature Details
Functional Description
Functional Description Interrupt Generation PCI Express* Power Management Dynamic Link Throttling Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) SERR# Generation Hot - Plug PCI Express* Lane Polarity Inversion Precision Time Measurement (PTM)
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Power Management
Power Management Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Features PCH S0 Low Power Power Management Sub-state PCH and System Power States SMI#/SCI Generation C-States Dynamic 38.4 MHz Clock Control Sleep States Event Input Signals and Their Usage ALT Access Mode System Power Supplies, Planes, and Signals Legacy Power Management Theory of Operation Reset Behavior
Features
PCH S0 Low Power
Power Management Sub-state
PCH and System Power States
SMI#/SCI Generation
C-States
Dynamic 38.4 MHz Clock Control
Sleep States
Event Input Signals and Their Usage
ALT Access Mode
System Power Supplies, Planes, and Signals
Legacy Power Management Theory of Operation
Reset Behavior
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Serial ATA (SATA)
Serial ATA (SATA) Signals Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signals Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description SATA 6 Gb/s Support SATA Feature Support Hot - Plug Operation Intel® Rapid Storage Technology (Intel® RST) Power Management Operation SATA Device Presence SATA LED Advanced Host Controller Interface (AHCI) Operation Enclosure Management (SGPIO Signals)
SATA 6 Gb/s Support
SATA Feature Support
Hot - Plug Operation
Intel® Rapid Storage Technology (Intel® RST)
Power Management Operation
SATA Device Presence
SATA LED
Advanced Host Controller Interface (AHCI) Operation
Enclosure Management (SGPIO Signals)
System Management Interface and SMLink
System Management Interface and SMLink Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Integrated USB-C Usage
Integrated USB-C Usage
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description SMBus Power Gating
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Host Controller SMBus Slave Interface
Host Controller
SMBus Slave Interface
SMBus Power Gating
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description VCCSPI Voltage (3.3 V or 1.8 V) Selection
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description SPI0 for Flash SPI0 Support for TPM
SPI0 for Flash
SPI0 Support for TPM
VCCSPI Voltage (3.3 V or 1.8 V) Selection
Touch Host Controller (THC)
Touch Host Controller (THC) Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Testability
Testability JTAG Boundry Scan Sideband Signals Intel® Trace Hub (Intel® TH) Direct Connect Interface (DCI)
JTAG
JTAG Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Boundry Scan Sideband Signals
Boundry Scan Sideband Signals Signal Description
Signal Description
Intel® Trace Hub (Intel® TH)
Direct Connect Interface (DCI)
Direct Connect Interface (DCI) Out Of Band (OOB) Hosting DCI USB 3.2 Hosting DCI.DBC
Out Of Band (OOB) Hosting DCI
USB 3.2 Hosting DCI.DBC
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Universal Serial Bus (USB)
Universal Serial Bus (USB) Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description AUX BIAS Control - USB Type-C Implementation with no Retimer Supported USB 2.0 Ports
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description eXtensible Host Controller Interface (xHCI) Controller USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
eXtensible Host Controller Interface (xHCI) Controller
USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
AUX BIAS Control - USB Type-C Implementation with no Retimer
Supported USB 2.0 Ports
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Signal Description Integrated Pull-ups and Pull-downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
I/O Signal Planes and States
Functional Description
GPIO Serial Expander
GPIO Serial Expander Signal Description Integrated Pull-ups and Pull-downs Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
Functional Description
Private Configuration Space Target Port ID
Miscellaneous Signals
Miscellaneous Signals Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States

Power Management Sub-state

S0ix State Enable

If a platform wants to disable certain S0ix states, BIOS can do so by modifying the LPM_​EN register. The mapping of S0ix states to bits in the LPM_​EN register are given below:

LPM_​EN Register Mapping

Bit Number

S0ix State

Required Implementation1

0

S0i2.0

None2

1

S0i2.1

None2

2

S0i2.2

EXT_​PWR_​GATE# controlled FET to gate internal power plane for the HSIO core and suspend logic.

3

S0i3.0

None2

4

S0i3.1

None2

5

S0i3.2

None2

6

S0i3.3

EXT_​PWR_​GATE# controlled FET to gate internal power plane for the HSIO core and suspend logic.

Notes:

  1. Other board capabilities such as power control for RTD3 cold may be implicitly required to satisfy requirements.
  2. For external bypass voltage selection, VNN_​CTRL and V1P05_​CTRL can be used to select the external bypass.

Power Management Sub-State

Base State

Sub-state

Internal Power Plane for Internal Units that not required during S0ix

Internal Power Plane for the HSIO Core and Suspend Logic

Internal Power Plane for Gated SRAMs and Integrated System Clock PLLs

S0i2.0

S0i2.1

OFF

ON

ON

S0i2.2

OFF

OFF

ON

S0i3.0

S0i3.1

OFF

ON

ON

S0i3.2

OFF

ON

ON

S0i3.3

OFF

OFF

ON

Note:S0ix.0 is a base state when all power planes are on. For S0i3.2, and S0i3.3, the internal active power planes will be margined down from 1.05 V to 0.95 V.

PCH and System Power States