Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
| ID | Date | Version | Classification |
|---|---|---|---|
| 631119 | 21/09/2021 00:00:00 | Public Content |
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Serial Peripheral Interface (SPI)
The PCH provides two Serial Peripheral Interfaces (SPI). The SPI0 interface consists of three Chip Select signals. The SPI0 interface can allow up to two flash memory devices (SPI0_CS0# and SPI0_CS1#) and one TPM device (SPI0_CS2#) to be connected to the PCH. The SPI0 interface support either 1.8 V or 3.3 V. The voltage is selected via a Hardware strap. Refer to VCCSPI Voltage (3.3 V or 1.8 V) Selection.
| Acronyms | Description |
|---|---|
| CLK | Clock |
| CS | Chip Select |
| FCBA | Flash Component Base Address |
| FIBA | Flash Initialization Base Address |
| FLA | Flash Linear Address |
| FMBA | Flash Master Base Address |
| FPSBA | Flash PCH Strap Base Address |
| FRBA | Flash Region Base Address |
| MDTBA | MIP Descriptor Table Base Address |
| MISO | Mater In Slave Out |
| MOSI | Mater Out Slave In |
| TPM | Trusted Platform Module |