Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
Signal Description
Display is divided between processor and PCH. The processor houses memory interface, display planes, pipes, and digital display interfaces/ports while the PCH has transcoder and analog display interface or port.
The PCH integrates digital display side band signals DDC bus, and Hot-Plug Detect signals even though digital display interfaces are moved to processor. There are two pairs of DDC Clock/Data, and Hot-Plug Detect signals on the PCH that correspond to digital display interface/ports.
The DDC (Digital Display Channel) bus is used for communication between the host system and display.
The Hot-Plug Detect (HPD) signal serves as an interrupt request for the sink device for DisplayPort* and HDMI*. It is a 3.3 V tolerant signal pin on the PCH.
| Name | Type | Description |
|---|---|---|
| GPP_E14 / DDSP_HPDA / DISP_MISCA | I | Display Port A: HPD Hot-Plug Detect |
| GPP_A18 / DDSP_HPDB / DISP_MISCB / I2S4_RXD | I | Display Port B: HPD Hot-Plug Detect |
| GPP_A19 / DDSP_HPD1 / DISP_MISC1 / I2S5_SCLK | I | TCP Port 1: HPD Hot-Plug Detect |
| GPP_A20 / DDSP_HPD2 / DISP_MISC2 / I2S5_SFRM | I | TCP Port 2: HPD Hot-Plug Detect |
| GPP_A14 / USB_OC1# / DDSP_HPD3 / I2S3_RXD / DISP_MISC3 / DMIC_CLK_B1 | I | TCP Port 3: HPD Hot-Plug Detect |
| GPP_A15 / USB_OC2# / DDSP_HPD4 / DISP_MISC4 / I2S4_SCLK | I | TCP Port 4: HPD Hot-Plug Detect |
| GPP_E22 / DDPA_CTRLCLK /DNX_FORCE_RELOAD | I/O | Display Port A: Control Clock |
| GPP_E23 / DDPA_CTRLDATA | I/O | Display Port A: Control Data |
| GPP_H16 / DDPB_CTRLCLK / PCIE_LNK_DOWN | I/O | Display Port B: Control Clock |
| GPP_H17 / DDPB_CTRLDATA | I/O | Display Port B: Control Data |
| GPP_E18 / DDP1_CTRLCLK / TBT_LSX0_TXD / BSSB_LS0_RX | I/O | TCP Port 1: Control Clock |
| GPP_E19 / DDP1_CTRLDATA / TBT_LSX0_RXD / BSSB_LS0_TX | I/O | TCP Port 1: Control Data |
| GPP_E20 / DDP2_CTRLCLK / TBT_LSX1_TXD / BSSB_LS1_RX | I/O | TCP Port 2: Control Clock |
| GPP_E21 / DDP2_CTRLDATA / TBT_LSX1_RXD / BSSB_LS1_TX | I/O | TCP Port 2: Control Data |
| GPP_D9 / ISH_SPI_CS# / DDP3_CTRLCLK / TBT_LSX2_TXD / BSSB_LS2_RX / GSPI2_CS0# | I/O | TCP Port 3: Control Clock |
| GPP_D10 / ISH_SPI_CLK / DDP3_CTRLDATA / TBT_LSX2_RXD / BSSB_LS2_TX / GSPI2_CLK | I/O | TCP Port 3: Control Data |
| GPP_D11 / ISH_SPI_MISO / DDP4_CTRLCLK / TBT_LSX3_TXD / BSSB_LS3_RX / GSPI2_MISO | I/O | TCP Port 4: Control Clock |
| GPP_D12 / ISH_SPI_MOSI / DDP4_CTRLDATA / TBT_LSX3_RXD / BSSB_LS3_TX / GSPI2_MOSI | I/O | TCP Port 4: Control Data |