| PCH-LP (UP3): - CLKOUT_PCIE_P0
- CLKOUT_PCIE_N0
- CLKOUT_PCIE_P1
- CLKOUT_PCIE_N1
- CLKOUT_PCIE_P2
- CLKOUT_PCIE_N2
- CLKOUT_PCIE_P3
- CLKOUT_PCIE_N3
- CLKOUT_PCIE_P4
- CLKOUT_PCIE_N4
- CLKOUT_PCIE_P5
- CLKOUT_PCIE_N5
- CLKOUT_PCIE_P6
- CLKOUT_PCIE_N6
PCH-LP (UP4): - CLKOUT_PCIE_P0
- CLKOUT_PCIE_N0
- CLKOUT_PCIE_P1
- CLKOUT_PCIE_N1
- CLKOUT_PCIE_P2
- CLKOUT_PCIE_N2
- CLKOUT_PCIE_P3
- CLKOUT_PCIE_N3
- CLKOUT_PCIE_P4
- CLKOUT_PCIE_N4
| O | Yes | PCI Express* Clock Output: Serial Reference 100 MHz PCIe* specification compliant differential output clocks to PCIe* devices - CLKOUT_PCIE_P/N [6:0] = Can be used for PCIe* Gen1/2/3 support
- CLKOUT_PCIE_P/N [4, 3, 0] = Must be used for PCIe* Gen4 support
|
| GPP_D4 / IMGCLKOUT0 / BK4 / SBK4 | O | | Imaging Clock : Clock for external camera sensor. |
| GPP_H20 / IMGCLKOUT1 | O | | Imaging Clock : Clock for external camera sensor. |
| GPP_H21 / IMGCLKOUT2 | O | | Imaging Clock : Clock for external camera sensor. |
| GPP_H22 / IMGCLKOUT3 | O | | Imaging Clock : Clock for external camera sensor. |
| GPP_H23 / IMGCLKOUT4 | O | | Imaging Clock : Clock for external camera sensor. |
| GPP_D15 / ISH_UART0_RTS# / GSPI2_CS1# / IMGCLKOUT5 | O | | Imaging Clock : Clock for external camera sensor. |
| PCH-LP (UP3): - GPP_D5 / SRCCLKREQ0#
- GPP_D6 / SRCCLKREQ1#
- GPP_D7 / SRCCLKREQ2#
- GPP_D8 / SRCCLKREQ3#
- GPP_H10 / SRCCLKREQ4#
- GPP_H11 / SRCCLKREQ5#
- GPP_F19 / SRCCLKREQ6#
PCH-LP (UP4): - GPP_D5 / SRCCLKREQ0#
- GPP_D6 / SRCCLKREQ1#
- GPP_D7 / SRCCLKREQ2#
- GPP_D8 / SRCCLKREQ3#
- GPP_H10 / SRCCLKREQ4#
- GPP_H11 / SRCCLKREQ5#
| I/O | | Clock Request: Serial Reference Clock request signals for PCIe* 100 MHz differential clocks |
| XTAL_IN | I | | Crystal Input: Input connection for 38.4 MHz crystal to PCH |
| XTAL_OUT | O | | Crystal Output: Output connection for 38.4 MHz crystal to PCH |
| XCLK_BIASREF | I/O | | Differential Clock Bias Reference: Used to set BIAS reference for differential clocks |
- SSC = Spread Spectrum Clocking. Intel does not recommend changing the Plan of Record and fully validated SSC default value set in BIOS Reference Code. The SSC level must only be adjusted for debugging or testing efforts and any Non POR configuration setting used are the sole responsibility of the customer.
- The SRCCLKREQ# signals can be configured to map to any of the PCH PCI Express* Root Ports while using any of the CLKOUT_PCIE_P/N differential pairs
|