Sleep States
Sleep State Overview
The PCH supports different sleep states (S4/S5), which are entered by methods such as setting the SLP_EN bit or due to a Power Button press. The entry to the Sleep states is based on several assumptions:
- The G3 state cannot be entered using any software mechanism. The G3 state indicates a complete loss of power.
Initiating Sleep State
Sleep states (S4/S5) are initiated by:
- Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state.
- Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies from the processor or on clocks other than the RTC clock.
- Assertion of the THERMTRIP# signal will cause a transition to the S5 state. This can occur when system is in the S0 state.
- Shutdown by integrated manageability functions (ASF/Intel CSME).
- Internal watchdog timer timeout events.
Sleep Types
| Sleep Type | Comment |
|---|
| S4 | The PCH asserts SLP_S3# and SLP_S4#. The motherboard uses the SLP_S4# signal to shut off the power to the memory subsystem and any other unneeded subsystem. Only devices needed to wake from this state should be powered. |
| S5 | The PCH asserts SLP_S3#, SLP_S4# and SLP_S5#. |
Exiting Sleep States
Sleep states (S4/S5) are exited based on wake events. The wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the storage subsystem may be shut off during a sleep state and have to be enabled using a GPIO pin before it can be used.
Upon exit from the PCH-controlled Sleep states, the WAK_STS bit is set. The possible causes of wake events (and their restrictions) are shown in the table below.
If the BATLOW# signal is asserted, the PCH does not attempt to wake from an S4/S5 state, nor will it exit from Deep Sx state, even if the power button is pressed. This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted are latched by the PCH, and the system wakes after BATLOW# is de-asserted. Causes of Wake Events
| Cause | How Enabled | Wake from Sx | Wake from Deep Sx | Wake from Sx After Power Loss2 | Wake from “Reset” Types3 |
|---|
| RTC Alarm | Set RTC_EN bit in PM1_EN_STS register. | Yes | Yes | Yes | No |
| Power Button | Always enabled as Wake event. | Yes | Yes | Yes | Yes |
| Any GPIOs except DSW GPIOs can be enabled for wake | Refer to Note 5 | Yes | No | No | No |
| LAN_WAKE# | Enabled natively (unless pin is configured to be in GPIO mode) | Yes | Yes | Yes | Yes |
| Intel® High Definition Audio | Event sets PME_B0_STS bit; PM_B0_EN must be enabled. Can not wake from S5 state if it was entered due to power failure or power button override. | Yes | No | Yes | No |
| Primary PME# | PME_B0_EN bit in GPE0_EN[127:96] register. | Yes | No | Yes | No |
| Secondary PME# | Set PME_EN bit in GPE0_EN[127:96] register. | Yes | No | Yes | No |
| PCI Express* WAKE# pin | PCIEXP_WAKE_DIS bit. | Yes | Yes | Yes | No |
| SMBALERT# | Refer to Note 4 | Yes | No | Yes | Yes |
| SMBus Slave Wake Message (01h) | Wake/SMI# command always enabled as a Wake event. SMBus Slave Message can wake the system from S4/S5, as well as from S5 due to Power Button Override. | Yes | No | Yes | Yes |
| SMBus Host Notify message received | HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPE0_STS register. | Yes | No | Yes | Yes |
| Intel® CSME Non-Maskable Wake | Always enabled as a wake event. | Yes | No | Yes | Yes |
| Integrated WoL Enable Override | WoL Enable Override bit (in Configuration Space). | Yes | Yes | Yes | Yes |
| Wake Alarm Device | WADT_EN in GPE0_EN[127:96] | Yes | Yes | No | No |
| ACPRESENT | ACPRESENT_WAKE_EN6 | No | Yes | No | No |
| USB connection in/after Deep Sx | GPE0_EN.USB_CON_DSX_EN+ | Refer to Note 7 | Yes | No | No |
- If BATLOW# signal is low, PCH will not attempt to wake from S4/S5 (nor will it exit Deep Sx), even if a valid wake event occurs. This prevents the system from waking when battery power is insufficient to wake the system. However, once BATLOW# de-asserts, the system will boot.
- This column represents what the PCH would honor as wake events but there may be enabling dependencies on the device side which are not enabled after a power loss.
- Reset Types include: Power Button override, Intel® CSME-initiated power button override, Intel CSME-initiated host partition reset with power down, Intel CSME Watchdog Timer, SMBus unconditional power down, processor thermal trip, PCH catastrophic temperature event.
- SMBALERT# signal is multiplexed with a GPIO pin that defaults to GPIO mode. Hence, SMBALERT# related wakes are possible only when this GPIO is configured in native mode, which means that BIOS must program this GPIO to operate in native mode before this wake is possible. Because GPIO configuration is in the resume well, wakes remain possible until one of the following occurs: BIOS changes the pin to GPIO mode, a G3 occurs or Deep Sx entry occurs.
- There are only 72 bits in the GPE registers to be assigned to GPIOs, though any of the GPIOs can trigger a wake, only those status of GPIO mapped to 1-tier scheme are directly accessible through the GPE status registers. For those GPIO mapped under 2-tier scheme, their status would be reflected under single master status, “GPIO_TIER2_SCI_STS” or GPE0_STS and further comparison needed to know which 2-tier GPI(s) has triggered the GPIO Tier 2 SCI.
- A change in ACPRESENT causes an exit from Deep Sx to Sx, but the system will not wake all the way to S0.
- Connection of a USB device can cause a wake from normal Sx as well. But that class of wakes is routed through PME_B0, not through this wake enable. The USB_CON_DSX_EN applies only to connection wakes while in Deep Sx or while in Sx after Deep Sx. Note: Sx after Deep Sx reached due to an Intel CSME wake from Deep Sx or due to ACPRESENT going high while in Deep Sx if Deep Sx is only enabled while on DC power. The following additional conditions are required for this wake to occur:
- The bit(s) in PM_CFG2.USB_DSX_PER_PORT_EN associated with the port(s) which experienced the connection must be set to ‘1’.
- DSX_CFG.USB_CON_DSX_MODE must be set to ‘1’, routing USB connection to generate a wake rather than be reflected out to a pin
|
PCI Express* WAKE# Signal and PME Event Message
PCI Express* ports can wake the platform from S4, S5, or Deep Sx using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS register.
PCI Express* WAKE# pin is an Output in S0ix states hence this pin cannot be used to wake up the system during S0ix states. PCI Express* ports and the processor have the ability to cause PME using messages.These are logically OR’d to set the single PCI_EXP_STS bit. When a PME message is received, the PCH will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the PCH can cause an SCI via GPE0_STS register.
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure.
The AFTERG3_EN bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure.
- PWRBTN#: PWRBTN# is always enabled as a wake event. When PCH_DPWROK is low (G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power returns (PCH_DPWROK goes high), the PWRBTN# signal will transition high due internal Pull-up, unless there is an on-board Pull-up/Pull-down) and the PWRBTN_STS bit is 0.
- RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_STS the RTC_STS bit is cleared when PCH_DPWROK goes low.
- Any enabled wake event that was preserved through the power failure.
DSW_PWROK going low would place the PCH into a G3 state.
Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Transitions Due to Power Failure
| State at Power Failure | AFTERG3_EN Bit | Transition when Power Returns and BATLOW# is inactive |
|---|
| S0 | 1 0 | S5 S0 |
| S4 | 1 0 | S4 S0 |
| S5 | 1 0 | S5 S0 |
| Deep S4 | 1 0 | Deep S4 S0 |
| Deep S5 | 1 0 | Deep S5 S0 |
- Entry state to Deep Sx is preserved through G3 allowing resume from Deep Sx to take appropriate path (that is, return to S4 or S5).
- G3 related Power Failure is defined as DSW_PWROK transition low.
|
Deep Sx
To minimize power consumption while in S4/S5, the PCH supports a lower power, lower featured version of these power states known as Deep Sx. In the Deep Sx state, the primary wells are powered off, while the Deep Sx Well (DSW) remains powered. A limited set of wake events are supported by the logic located in the DSW.
The Deep Sx capability and the SUSPWRDNACK pin functionality are mutually exclusive.
A combination of conditions is required for entry into Deep Sx. PMC firmware is responsible for enforcing these requirements. The requirements, all of which must be met to enter Deep Sx, are detailed below :
- RTCPMCFG.INT_SUS_PD_EN = 1
- Intel CSME must program this bit prior to initiating CMOFF or CM3-PG entry
- Intel CSME in CMOFF or CM3-PG
- Deep Sx conditions are checked during CMOFF and CM3-PG entry. If Deep Sx entry would have been allowed if the ACPRESENT# signal had been high, PMC FW will enable ACPRESENT# as an interrupt source, initiating Deep Sx entry if the power source changes to match the required state
- Host in S4, or S5 and combination of S-state and power source matches the host policy bits
- ( (S4AC_GATE_SUS AND S4) OR
OR
- ((ACPRESENT = 0) AND ( (S4DC_GATE_SUS AND S4) OR (S5DC_GATE_SUS AND S5)))
- Either Deep Sx entry is not determined by BATLOW# state or BATLOW# is asserted
- REQ_BATLOW_DSX == ‘0’ OR BATLOW# == ‘0’
- Either Deep Sx entry is not determined by connectivity wake enable or connectivity wake is enabled
- REQ_CNV_NOWAKE_DSX == ‘0’ OR SLP_WLAN_VAL == ‘0’
Supported Deep Sx Policy Configurations
| Configuration | S4DC_GATE_SUS | S4AC_GATE_SUS | S5DC_GATE_SUS | S5AC_GATE_SUS |
|---|
- Enabled in S5 Battery Only (ACPRESENT = 0)
| 0 | 0 | 1 | 0 |
- Enabled in S5 (ACPRESENT not considered)
| 0 | 0 | 1 | 1 |
- Enabled in S4 and S5 when on Battery only (ACPRESENT = 0)
| 1 | 0 | 1 | 0 |
- Enabled in S4 and S5 (ACPRESENT not considered)
| 1 | 1 | 1 | 1 |
- Enabled in , S4, and S5 when on Battery only (ACPRESENT = 0)
| 1 | 0 | 1 | 0 |
- Enabled in , S4, and S5 (ACPRESENT not considered)
| 1 | 1 | 1 | 1 |
- Deep S4 / S5 disabled
| 0 | 0 | 0 | 0 |
| All other configurations are RESERVED. |
The PCH also performs a SUSWARN#/SUSACK# handshake to ensure the platform is ready to enter Deep Sx. The PCH asserts SUSWARN# as notification that it is about to enter Deep Sx. Before the PCH proceeds and asserts SLP_SUS#, the PCH waits for SUSACK# to assert.
While in Deep Sx, the PCH monitors and responds to a limited set of wake events (RTC Alarm, Power Button and WAKE#). Upon sensing an enabled Deep Sx wake event, the PCH brings up the primary well by de-asserting SLP_SUS#.
Deep Sx Wake Events
| Event | Enable |
|---|
| RTC Alarm | RTC_EN bit in PM1_EN_STS Register |
| Power Button | Always enabled |
| PCIe* WAKE# pin | PCIEXP_WAKE_DIS |
| Wake Alarm Device | WADT_EN in GPE0_EN |
| LAN_WAKE# | Enabled natively (unless the pin is configured to be in the GPIO mode) |
ACPRESENT has some behaviors that are different from the other Deep Sx wake events. If the Intel CSME has enabled ACPRESENT as a wake event then it behaves just like any other Intel CSME Deep Sx wake event. However, even if ACPRESENT wakes are not enabled, if the Host policies indicate that Deep Sx is only supported when on battery, then ACPRESENT going high will cause the PCH to exit Deep Sx. In this case, the primary wells gets powered up and the platform remains in Sx/M-Off or Sx/M3-PGS3/M-Off. If ACPRESENT subsequently drops (before any Host or Intel® CSME wake events are detected), the PCH will re-enter Deep Sx.