The Serial Peripheral Interface (SPI0) supports two SPI flash devices via two chip select (SPI0_​CS0# and SPI0_​CS1#). The maximum size of flash supported is determined by the SFDP-discovered addressing capability of each device. Each component can be up to 16 MB (32 MB total addressable) using 3-byte addressing. Each component can be up to 64 MB (128 MB total addressable) using 4-byte addressing. Another chip select (SPI0_​CS2#) is also available and only used for TPM on SPI support. PCH drives the SPI0 interface clock at either 20 MHz, 33 MHz, or 50 MHz and will function with SPI flash devices that support at least one of these frequencies. The SPI interface supports either 3.3 V or 1.8 V.

A SPI0 flash device supporting SFDP (Serial Flash Discovery Parameter) is required for all PCH design. A SPI0 flash device on SPI0_​CS0# with a valid descriptor MUST be attached directly to the PCH.

The PCH supports fast read which consist of:

1. Dual Output Fast Read (Single Input Dual Output)
2. Dual I/O Fast Read (Dual Input Dual Output)
3. Quad Output Fast Read (Single Input Quad Output)
4. Quad I/O Fast Read (Quad Input Quad Output)

The PCH SPI0 has a third chip select SPI0_​CS2# for TPM support over SPI. The TPM on SPI0 will use SPI0_​CLK, SPI0_​MISO, SPI0_​MOSI and SPI0_​CS2# SPI signals.

SPI0 Supported Features

• Descriptor Mode

  Descriptor Mode is required for all SKUs of the PCH. Non-Descriptor Mode is not supported.

• SPI0 Flash Regions

  In Descriptor Mode the Flash is divided into five separate regions.

  SPI0 Flash Regions

  Region	Content
  0	Flash Descriptor
  1	BIOS
  2	Intel® CSME
  3	Gigabit Ethernet
  4	Platform Data
  5	EC

  Only four masters can access the regions: Host processor running BIOS code, Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, Intel^® CSME , and the EC.

  The Flash Descriptor and Intel^® CSME region are the only required regions. The Flash Descriptor has to be in region 0 and region 0 must be located in the first sector of Device 0 (Offset 0). All other regions can be organized in any order.

  Regions can extend across multiple components, but must be contiguous.

  Flash Region Sizes

  SPI0 flash space requirements differ by platform and configuration. The Flash Descriptor requires one 4-KB or larger block. GbE requires two 4-KB or larger blocks. The amount of flash space consumed is dependent on the erase granularity of the flash part and the platform requirements for the Intel^® CSME and BIOS regions. The Intel^® CSME region contains firmware to support Intel Active Management Technology and other Intel^® CSME capabilities.

  Region Size Versus Erase Granularity of Flash Components 

  Region	Size with 4-KB Blocks	Size with 8-KB Blocks	Size with 64-KB Blocks
  Descriptor	4 KB	8 KB	64 KB
  GbE	8 KB	16 KB	128 KB
  BIOS	Varies by Platform	Varies by Platform	Varies by Platform
  Intel® CSME	Varies by Platform	Varies by Platform	Varies by Platform
  EC	Varies by Platform	Varies by Platform	Varies by Platform

Flash Descriptor

The bottom sector of the flash component 0 contains the Flash Descriptor. The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI0 flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the first block. The flash descriptor requires its own block at the bottom of memory (00h). The information stored in the Flash Descriptor can only be written during the manufacturing process as its read/write permissions must be set to read only when the computer leaves the manufacturing floor.

The Flash Descriptor is made up of eleven sections as shown in the figure below.

• The Flash signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning. The data at the bottom of the flash (offset 10h) must be 0FF0A55Ah in order to be in Descriptor mode.
• The Descriptor map has pointers to the other five descriptor sections as well as the size of each.
• The component section has information about the SPI0 flash in the system including: the number of components, density of each, invalid instructions (such as chip erase), and frequencies for read, fast read and write/erase instructions.
• The Region section points to the three other regions as well as the size of each region.
• The master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requester ID.
• The processor and PCH Soft Strap sections contain processor and PCH configurable parameters.
• The Reserved region between the top of the processor strap section and the bottom of the OEM Section is reserved for future chipset usages.
• The Descriptor Upper MAP determines the length and base address of the Management Engine VSCC Table.
• The Management Engine VSCC Table holds the JEDEC ID and the VSCC information of the entire SPI0 Flash supported by the NVM image.
• OEM Section is 256 bytes reserved at the top of the Flash Descriptor for use by OEM.

• Descriptor Master Region

  The master region defines read and write access setting for each region of the SPI0 device. The master region recognizes four masters: BIOS, Gigabit Ethernet, Management Engine, and EC. Each master is only allowed to do direct reads of its primary regions.

  Region Access Control Table

  Master Read/Write Access
  Region	Processor and BIOS	Intel® CSME	GbE Controller	EC
  BIOS	Read/Write	N/A	Read/Write	Note
  Intel® CSME	N/A	Read/Write	Read	N/A
  Gigabit Ethernet	N/A	N/A	Read/Write	N/A
  EC	Read	N/A	N/A	Read/Write
  Note:Optional BIOS access to the EC region.

• Flash Descriptor Processor Complex Soft Strap Section

  Region Name	Starting Address
  Signature	10h
  Component FCBA	30h
  Regions FRBA	40h
  Masters FMBA	80h
  PCH Straps FPSBA	100h
  MDTBA	C00h
  PMC Straps	C14h
  Processor Straps	C2Ch
  Intel® CSME Straps	C3Ch
  Register Init FIBA	340h

Flash Access

There are two types of accesses: Direct Access and Program Register Accesses.

• Direct Access
  • Masters are allowed to do direct read only of their primary region
    • Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet controller. Gigabit Ethernet software must use Program Registers to access the Gigabit Ethernet region.
  • Master's Host or Management Engine virtual read address is converted into the SPI0 Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers

    Direct Access Security

  • Requester ID of the device must match that of the primary Requester ID in the Master Section
  • Calculated Flash Linear Address must fall between primary region base/limit
  • Direct Write not allowed
  • Direct Read Cache contents are reset to 0's on a read from a different master

• Program Register Access
  • Program Register Accesses are not allowed to cross a 4-KB boundary and can not issue a command that might extend across two components
  • Software programs the FLA corresponding to the region desired
    • Software must read the devices Primary Region Base/Limit address to create a FLA.

  Register Access Security

  • Only primary region masters can access the registers